keepass-plugin-onedrivesync
|
2.1.2.2-1 |
1 |
0.00
|
KeePass plugin to allows syncing of KeePass databases stored on OneDrive Personal, OneDrive for Business or SharePoint. |
XLWZ
|
2021-12-12 02:38 (UTC) |
streamspeed
|
2.0.0-1 |
0 |
0.00
|
A simple Rust program that prints the transfer speed of stdin |
xlash123
|
2022-09-24 20:55 (UTC) |
zoomx
|
0.0.1-1 |
2 |
1.00
|
Screen magnifying zoom utility for X11 |
xklo
|
2021-02-21 02:39 (UTC) |
zenbooru
|
0.4.6-1 |
3 |
0.00
|
A standalone client for image boards that supports Gelbooru v0.2, Danbooru (v1 & v2), Moebooru, and booru.org sites. |
xkero
|
2015-07-29 18:47 (UTC) |
yosys-f4pga-plugins-git
|
1.0.0_7_g59ff1e6_23_g3a95697_17_g00b887b.r957.gc6bc59e-1 |
0 |
0.00
|
Plugins for Yosys developed as part of the F4PGA project. |
xiretza
|
2022-05-25 13:21 (UTC) |
vtr-git
|
8.0.0.r3718.g265904830-1 |
1 |
0.00
|
Open Source CAD Flow for FPGA Research |
xiretza
|
2021-06-04 08:39 (UTC) |
vivado
|
2022.2-1 |
13 |
0.24
|
FPGA/CPLD design suite for Xilinx devices |
xiretza
|
2022-10-25 16:00 (UTC) |
v2x-git
|
0.0.r616.g1325cb3-1 |
0 |
0.00
|
A tool for converting specialized annotated Verilog models into XML |
xiretza
|
2022-05-14 18:46 (UTC) |
usb2sniffer-qt-git
|
r160.cf74d49-1 |
0 |
0.00
|
LambdaConcept lcsniff software for USB2Sniffer hardware |
xiretza
|
2020-10-01 09:24 (UTC) |
uhdm-git
|
r1270.ad9a41e-2 |
0 |
0.00
|
A complete modeling of the IEEE SystemVerilog Object Model |
xiretza
|
2022-02-20 15:43 (UTC) |
tinycmmc-git
|
r50.32eaa5b-1 |
0 |
0.00
|
Tiny CMake Module Collections |
xiretza
|
2022-06-27 09:06 (UTC) |
ternimal-git
|
r5.2eea4f4-2 |
4 |
0.00
|
Simulate a lifeform in the terminal |
xiretza
|
2017-11-05 15:28 (UTC) |
surelog-git
|
r4745.f96768e1f-1 |
0 |
0.00
|
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. |
xiretza
|
2022-05-20 18:46 (UTC) |
stickerpicker-git
|
r78.99ced88-1 |
1 |
0.00
|
Element sticker picker widget |
xiretza
|
2022-05-23 17:52 (UTC) |
spirv-headers-git
|
1:1.3.236.0.r4.g34d0464-1 |
3 |
0.00
|
SPIR-V header files Git version |
xiretza
|
2022-12-24 11:59 (UTC) |
soapysdr-git
|
3:0.8.1.r25.g9cbaa3c-1 |
22 |
0.00
|
Vendor and platform neutral SDR support library |
xiretza
|
2022-03-21 07:46 (UTC) |
shelltestrunner
|
1.9-1 |
0 |
0.00
|
Easy, repeatable testing of CLI programs/commands |
xiretza
|
2022-01-19 19:35 (UTC) |
sgp4-git
|
r301.ca9d4d9-1 |
2 |
0.00
|
SGP4 library |
xiretza
|
2021-04-24 14:41 (UTC) |
sdrangel-git
|
7.6.2.r11.3c7e7974a-1 |
11 |
0.04
|
Qt5/OpenGL SDR and signal analyzer frontend. |
xiretza
|
2022-08-24 17:14 (UTC) |
riscv64-unknown-elf-picolibc
|
1.8-1 |
0 |
0.00
|
Fork of newlib with stdio bits from avrlibc |
xiretza
|
2023-01-29 20:16 (UTC) |
rapidyaml-git
|
0.2.3.r21.gefc8b0e-1 |
2 |
0.06
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2021-12-27 19:15 (UTC) |
rapidwright
|
2022.2.0_beta-1 |
0 |
0.00
|
Build Customized FPGA Implementations for Vivado |
xiretza
|
2022-12-23 18:04 (UTC) |
quicklogic-timings-importer-git
|
r75.eec0737-2 |
0 |
0.00
|
Importer of timing data from Quicklogic EOS-S3 to SDF |
xiretza
|
2022-05-15 07:08 (UTC) |
qlf_fasm-git
|
r44.e5d0915-1 |
0 |
0.00
|
FASM to/from bitstream converter for QuickLogic qlf FPGA device family |
xiretza
|
2022-05-14 18:30 (UTC) |
python-xc-fasm-git
|
r72.e12f313-1 |
0 |
0.00
|
Library to convert FASM files to bitstream |
xiretza
|
2021-01-21 10:14 (UTC) |
python-vtr-xml-utils-git
|
r86.d6ba1f1-2 |
0 |
0.00
|
Utilities for working with VtR XML Files |
xiretza
|
2021-12-28 15:49 (UTC) |
python-tinyfpgab-git
|
r80.e8f9150-1 |
0 |
0.00
|
Programmer for the TinyFPGA B2 boards |
xiretza
|
2021-01-21 09:49 (UTC) |
python-textx
|
3.1.1-1 |
0 |
0.00
|
Python library for building Domain-Specific Languages and parsers |
xiretza
|
2023-02-19 16:06 (UTC) |
python-sphinxextensions
|
0.2.0-1 |
0 |
0.00
|
Extensions for the Sphinx documentation tool |
xiretza
|
2021-07-12 12:27 (UTC) |
python-simplematrixbotlib
|
2.7.2-1 |
0 |
0.00
|
An easy to use bot library for the Matrix ecosystem written in Python |
xiretza
|
2022-10-15 09:13 (UTC) |
python-sdf-timing-git
|
r118.5b9dc79-1 |
0 |
0.00
|
Python library for working Standard Delay Format (SDF) Timing Annotation files |
xiretza
|
2021-04-13 17:22 (UTC) |
python-rapidyaml-git
|
0.2.3.r21.gefc8b0e-1 |
2 |
0.06
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2021-12-27 19:15 (UTC) |
python-quicklogic-fasm-utils-git
|
r13.3d6a375-1 |
0 |
0.00
|
A set of tools for creating FASM assemblers for the Symbiflow project |
xiretza
|
2022-05-14 18:04 (UTC) |
python-quicklogic-fasm-git
|
r56.fafa623-1 |
0 |
0.00
|
Tools, scripts and resources for generating a bitstream from FASM files for QuickLogic FPGAs |
xiretza
|
2022-05-14 18:03 (UTC) |
python-pyvhdlmodel-git
|
0.14.1.r0.gc6fe167-1 |
0 |
0.00
|
An abstract VHDL language model written in Python |
xiretza
|
2021-12-17 18:11 (UTC) |
python-pytooling-terminalui
|
1.5.9-1 |
0 |
0.00
|
A set of helpers to implement a text user interface (TUI) in a terminal |
xiretza
|
2022-09-20 19:25 (UTC) |
python-pytooling
|
3.0.0-2 |
0 |
0.00
|
A powerful collection of arbitrary useful classes, decorators, meta-classes and exceptions |
xiretza
|
2023-03-13 18:36 (UTC) |
python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
|
Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-serv-git
|
2020.08.r38.g2428c0c-1 |
1 |
0.00
|
Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-rocket-git
|
2020.08.r1.gfe810b8-1 |
1 |
0.00
|
Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-picorv32-git
|
2020.08.r1.g8bdce32-1 |
0 |
0.00
|
Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
python-pythondata-cpu-mor1kx-git
|
2020.08.r3.gff01892-1 |
0 |
0.00
|
Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-pythondata-cpu-minerva-git
|
2020.08.r4.g2a69b7f-1 |
0 |
0.00
|
Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
python-pythondata-cpu-microwatt-git
|
2020.08.r219.gd695ff9-1 |
0 |
0.00
|
Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-pythondata-cpu-lm32-git
|
2020.08.r1.g6344000-1 |
0 |
0.00
|
Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
|
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-blackparrot-git
|
2020.08.r18.gba50883f-1 |
0 |
0.00
|
Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
python-pyghdl-git
|
1.0.0.r946.7e41be2da-1 |
0 |
0.00
|
Python binding for GHDL and high-level APIs |
xiretza
|
2021-12-27 17:38 (UTC) |
python-pydecor-git
|
2.0.0.r11.gd506ca8-1 |
0 |
0.00
|
Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
python-pyattributes
|
2.5.1-1 |
0 |
0.00
|
Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |