|
python-itertree
|
1.0.5-1 |
0 |
0.00
|
Python tree structure for data storage and iterations |
xiretza
|
2023-07-16 14:47 (UTC) |
|
python-litedram-git
|
2020.08.r101.g1117068-1 |
0 |
0.00
|
A small footprint and configurable DRAM core for LiteX |
xiretza
|
2020-11-17 11:39 (UTC) |
|
python-liteeth-git
|
2020.04.r34.g0624256-1 |
0 |
0.00
|
A small footprint and configurable Ethernet core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-liteiclink-git
|
2020.08.r83.g3d1165b-1 |
0 |
0.00
|
Small footprint and configurable inter chip communication cores for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litejesd204b-git
|
2020.08.r1.g1e88fa8-1 |
0 |
0.00
|
A small footprint and configurable JESD204B core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litepcie-git
|
2020.08.r40.g5e88ab6-1 |
0 |
0.00
|
A small footprint and configurable PCIe core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litesata-git
|
2020.08.r66.ge850b72-1 |
0 |
0.00
|
A small footprint and configurable SATA core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litescope-git
|
2020.08.r10.g94e2d15-1 |
0 |
0.00
|
A small footprint and configurable embedded logic analyzer for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litesdcard-git
|
2020.08.r14.g9e267a5-1 |
0 |
0.00
|
A small footprint and configurable SDCard core for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
|
python-litevideo-git
|
2020.04.r0.g41f3014-1 |
0 |
0.00
|
Small footprint and configurable video cores for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
|
python-litex-boards-git
|
2020.12.r26.gbee71da-1 |
0 |
0.00
|
LiteX supported boards |
xiretza
|
2021-01-22 08:58 (UTC) |
|
python-litex-git
|
2020.04.r867.g5097b7ae-1 |
0 |
0.00
|
A Migen/MiSoC based Core/SoC builder |
xiretza
|
2020-11-17 11:41 (UTC) |
|
python-prjxray-git
|
r3800.3418f9b5-1 |
0 |
0.00
|
Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
|
python-pyattributes
|
2.5.1-1 |
0 |
0.00
|
Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |
|
python-pydecor-git
|
2.0.0.r11.gd506ca8-1 |
0 |
0.00
|
Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
|
python-pyghdl-git
|
3.0.0.r193.97df73f72-1 |
0 |
0.00
|
Python binding for GHDL and high-level APIs |
xiretza
|
2023-05-09 19:40 (UTC) |
|
python-pythondata-cpu-blackparrot-git
|
2020.08.r18.gba50883f-1 |
0 |
0.00
|
Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
|
python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
|
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
|
python-pythondata-cpu-lm32-git
|
2020.08.r1.g6344000-1 |
0 |
0.00
|
Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
|
python-pythondata-cpu-microwatt-git
|
2020.08.r219.gd695ff9-1 |
0 |
0.00
|
Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
|
python-pythondata-cpu-minerva-git
|
2020.08.r4.g2a69b7f-1 |
0 |
0.00
|
Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
|
python-pythondata-cpu-mor1kx-git
|
2020.08.r3.gff01892-1 |
0 |
0.00
|
Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
|
python-pythondata-cpu-picorv32-git
|
2020.08.r1.g8bdce32-1 |
0 |
0.00
|
Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
|
python-pythondata-cpu-rocket-git
|
2020.08.r1.gfe810b8-1 |
1 |
0.00
|
Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
|
python-pythondata-cpu-serv-git
|
2020.08.r38.g2428c0c-1 |
1 |
0.00
|
Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
|
python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
|
Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
|
python-pytooling
|
6.0.1-1 |
0 |
0.00
|
A powerful collection of arbitrary useful classes, decorators, meta-classes and exceptions |
xiretza
|
2024-03-03 14:46 (UTC) |
|
python-pyvhdlmodel-git
|
0.25.1.r0.g3776f27-2 |
0 |
0.00
|
An abstract VHDL language model written in Python |
xiretza
|
2023-05-07 16:10 (UTC) |
|
python-quicklogic-fasm-git
|
r56.fafa623-1 |
0 |
0.00
|
Tools, scripts and resources for generating a bitstream from FASM files for QuickLogic FPGAs |
xiretza
|
2022-05-14 18:03 (UTC) |
|
python-quicklogic-fasm-utils-git
|
r13.3d6a375-1 |
0 |
0.00
|
A set of tools for creating FASM assemblers for the Symbiflow project |
xiretza
|
2022-05-14 18:04 (UTC) |
|
python-rapidyaml-git
|
0.5.0.r14.g6a5a07f-1 |
2 |
0.00
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2023-05-14 13:45 (UTC) |
|
python-sdf-timing-git
|
r118.5b9dc79-1 |
0 |
0.00
|
Python library for working Standard Delay Format (SDF) Timing Annotation files |
xiretza
|
2021-04-13 17:22 (UTC) |
|
python-simplematrixbotlib
|
2.11.0-1 |
0 |
0.00
|
An easy to use bot library for the Matrix ecosystem written in Python |
xiretza
|
2024-03-03 14:34 (UTC) |
|
python-sphinxextensions
|
0.2.0-1 |
0 |
0.00
|
Extensions for the Sphinx documentation tool |
xiretza
|
2021-07-12 12:27 (UTC) |
|
python-textx
|
4.0.1-1 |
0 |
0.00
|
Python library for building Domain-Specific Languages and parsers |
xiretza
|
2024-03-03 14:06 (UTC) |
|
python-tinyfpgab-git
|
r80.e8f9150-1 |
0 |
0.00
|
Programmer for the TinyFPGA B2 boards |
xiretza
|
2021-01-21 09:49 (UTC) |
|
python-vtr-xml-utils-git
|
r86.d6ba1f1-2 |
0 |
0.00
|
Utilities for working with VtR XML Files |
xiretza
|
2021-12-28 15:49 (UTC) |
|
python-xc-fasm-git
|
r72.e12f313-1 |
0 |
0.00
|
Library to convert FASM files to bitstream |
xiretza
|
2021-01-21 10:14 (UTC) |
|
qlf_fasm-git
|
r44.e5d0915-1 |
0 |
0.00
|
FASM to/from bitstream converter for QuickLogic qlf FPGA device family |
xiretza
|
2022-05-14 18:30 (UTC) |
|
quicklogic-timings-importer-git
|
r75.eec0737-2 |
0 |
0.00
|
Importer of timing data from Quicklogic EOS-S3 to SDF |
xiretza
|
2022-05-15 07:08 (UTC) |
|
rapidwright
|
2023.2.1_beta-1 |
0 |
0.00
|
Build Customized FPGA Implementations for Vivado |
xiretza
|
2024-03-03 14:54 (UTC) |
|
rapidyaml-git
|
0.5.0.r14.g6a5a07f-1 |
2 |
0.00
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2023-05-14 13:45 (UTC) |
|
riscv64-unknown-elf-picolibc
|
1.8.6-1 |
0 |
0.00
|
Fork of newlib with stdio bits from avrlibc |
xiretza
|
2024-03-03 13:35 (UTC) |
|
sdrangel-git
|
7.18.1.r28.29a8d21ba-1 |
15 |
0.16
|
Qt5/OpenGL SDR and signal analyzer frontend. |
xiretza
|
2024-03-03 18:32 (UTC) |
|
sgp4-git
|
r301.ca9d4d9-1 |
3 |
0.16
|
SGP4 library |
xiretza
|
2021-04-24 14:41 (UTC) |
|
shelltestrunner
|
1.10-2 |
0 |
0.00
|
Easy, repeatable testing of CLI programs/commands |
xiretza
|
2024-03-20 17:15 (UTC) |
|
soapysdr-git
|
3:0.8.1.r25.g9cbaa3c-1 |
22 |
0.00
|
Vendor and platform neutral SDR support library |
xiretza
|
2022-03-21 07:46 (UTC) |
|
spirv-headers-git
|
1:1.3.280.0.r3.g4f7b471-1 |
5 |
0.04
|
SPIR-V header files Git version |
xiretza
|
2024-04-01 19:58 (UTC) |
|
stickerpicker-git
|
r78.99ced88-1 |
1 |
0.00
|
Element sticker picker widget |
xiretza
|
2022-05-23 17:52 (UTC) |
|
surelog-git
|
1.75.r1.ge83d01f-1 |
0 |
0.00
|
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. |
xiretza
|
2023-09-24 20:37 (UTC) |