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python-cmake-build-extension-git
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0.5.1.r13.g856f0e0-1 |
0 |
0.00
|
Setuptools extension to build and package CMake projects |
xiretza
|
2023-05-18 10:57 (UTC) |
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python-constraint-git
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2.0.0b3.r10.g2357471-1 |
0 |
0.00
|
Solvers for Constraint Satisfaction Problems (CSPs) over finite domains in simple and pure Python |
xiretza
|
2023-09-24 14:23 (UTC) |
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python-cryptography-fernet-wrapper
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1.0.3-2 |
1 |
0.00
|
A wrapper for cryptography.fernet |
xiretza
|
2023-09-17 11:45 (UTC) |
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python-fasm-git
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0.0.2.r98.g9a73d70-4 |
0 |
0.00
|
FPGA Assembly (FASM) Parser and Generation library |
xiretza
|
2022-06-17 07:56 (UTC) |
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python-flatbuffers-git
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1:2.0.6.r130.g6e279164-1 |
0 |
0.00
|
An efficient cross platform serialization library for Python |
xiretza
|
2022-07-31 15:45 (UTC) |
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python-gpsoauth
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1.0.3-1 |
2 |
0.00
|
A python client library for Google Play Services OAuth. |
xiretza
|
2023-10-01 17:39 (UTC) |
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python-itertree
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1.0.5-1 |
0 |
0.00
|
Python tree structure for data storage and iterations |
xiretza
|
2023-07-16 14:47 (UTC) |
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python-litedram-git
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2020.08.r101.g1117068-1 |
0 |
0.00
|
A small footprint and configurable DRAM core for LiteX |
xiretza
|
2020-11-17 11:39 (UTC) |
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python-liteeth-git
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2020.04.r34.g0624256-1 |
0 |
0.00
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A small footprint and configurable Ethernet core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-liteiclink-git
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2020.08.r83.g3d1165b-1 |
0 |
0.00
|
Small footprint and configurable inter chip communication cores for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litejesd204b-git
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2020.08.r1.g1e88fa8-1 |
0 |
0.00
|
A small footprint and configurable JESD204B core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litepcie-git
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2020.08.r40.g5e88ab6-1 |
0 |
0.00
|
A small footprint and configurable PCIe core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litesata-git
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2020.08.r66.ge850b72-1 |
0 |
0.00
|
A small footprint and configurable SATA core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litescope-git
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2020.08.r10.g94e2d15-1 |
0 |
0.00
|
A small footprint and configurable embedded logic analyzer for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
|
python-litesdcard-git
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2020.08.r14.g9e267a5-1 |
0 |
0.00
|
A small footprint and configurable SDCard core for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-litevideo-git
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2020.04.r0.g41f3014-1 |
0 |
0.00
|
Small footprint and configurable video cores for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-litex-boards-git
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2020.12.r26.gbee71da-1 |
0 |
0.00
|
LiteX supported boards |
xiretza
|
2021-01-22 08:58 (UTC) |
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python-litex-git
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2020.04.r867.g5097b7ae-1 |
0 |
0.00
|
A Migen/MiSoC based Core/SoC builder |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-prjxray-git
|
r3800.3418f9b5-1 |
0 |
0.00
|
Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
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python-pyattributes
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2.5.1-1 |
0 |
0.00
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Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |
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python-pydecor-git
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2.0.0.r11.gd506ca8-1 |
0 |
0.00
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Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
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python-pyghdl-git
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3.0.0.r193.97df73f72-1 |
0 |
0.00
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Python binding for GHDL and high-level APIs |
xiretza
|
2023-05-09 19:40 (UTC) |
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python-pythondata-cpu-blackparrot-git
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2020.08.r18.gba50883f-1 |
0 |
0.00
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Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
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python-pythondata-cpu-cv32e40p-git
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2020.08.r1.gb8fe3c4-1 |
0 |
0.00
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Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
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python-pythondata-cpu-lm32-git
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2020.08.r1.g6344000-1 |
0 |
0.00
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Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
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python-pythondata-cpu-microwatt-git
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2020.08.r219.gd695ff9-1 |
0 |
0.00
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Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
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python-pythondata-cpu-minerva-git
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2020.08.r4.g2a69b7f-1 |
0 |
0.00
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Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
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python-pythondata-cpu-mor1kx-git
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2020.08.r3.gff01892-1 |
0 |
0.00
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Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
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python-pythondata-cpu-picorv32-git
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2020.08.r1.g8bdce32-1 |
0 |
0.00
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Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
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python-pythondata-cpu-rocket-git
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2020.08.r1.gfe810b8-1 |
1 |
0.00
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Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-serv-git
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2020.08.r38.g2428c0c-1 |
1 |
0.00
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Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-vexriscv-git
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2020.08.r1.g2962f4a-1 |
0 |
0.00
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Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pytooling
|
5.0.0-1 |
0 |
0.00
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A powerful collection of arbitrary useful classes, decorators, meta-classes and exceptions |
xiretza
|
2023-07-16 14:34 (UTC) |
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python-pyvhdlmodel-git
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0.25.1.r0.g3776f27-2 |
0 |
0.00
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An abstract VHDL language model written in Python |
xiretza
|
2023-05-07 16:10 (UTC) |
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python-quicklogic-fasm-git
|
r56.fafa623-1 |
0 |
0.00
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Tools, scripts and resources for generating a bitstream from FASM files for QuickLogic FPGAs |
xiretza
|
2022-05-14 18:03 (UTC) |
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python-quicklogic-fasm-utils-git
|
r13.3d6a375-1 |
0 |
0.00
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A set of tools for creating FASM assemblers for the Symbiflow project |
xiretza
|
2022-05-14 18:04 (UTC) |
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python-rapidyaml-git
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0.5.0.r14.g6a5a07f-1 |
2 |
0.00
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2023-05-14 13:45 (UTC) |
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python-sdf-timing-git
|
r118.5b9dc79-1 |
0 |
0.00
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Python library for working Standard Delay Format (SDF) Timing Annotation files |
xiretza
|
2021-04-13 17:22 (UTC) |
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python-simplematrixbotlib
|
2.10.1-1 |
0 |
0.00
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An easy to use bot library for the Matrix ecosystem written in Python |
xiretza
|
2023-09-24 14:32 (UTC) |
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python-sphinxextensions
|
0.2.0-1 |
0 |
0.00
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Extensions for the Sphinx documentation tool |
xiretza
|
2021-07-12 12:27 (UTC) |
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python-textx
|
3.1.1-1 |
0 |
0.00
|
Python library for building Domain-Specific Languages and parsers |
xiretza
|
2023-02-19 16:06 (UTC) |
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python-tinyfpgab-git
|
r80.e8f9150-1 |
0 |
0.00
|
Programmer for the TinyFPGA B2 boards |
xiretza
|
2021-01-21 09:49 (UTC) |
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python-vtr-xml-utils-git
|
r86.d6ba1f1-2 |
0 |
0.00
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Utilities for working with VtR XML Files |
xiretza
|
2021-12-28 15:49 (UTC) |
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python-xc-fasm-git
|
r72.e12f313-1 |
0 |
0.00
|
Library to convert FASM files to bitstream |
xiretza
|
2021-01-21 10:14 (UTC) |
|
qlf_fasm-git
|
r44.e5d0915-1 |
0 |
0.00
|
FASM to/from bitstream converter for QuickLogic qlf FPGA device family |
xiretza
|
2022-05-14 18:30 (UTC) |
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quicklogic-timings-importer-git
|
r75.eec0737-2 |
0 |
0.00
|
Importer of timing data from Quicklogic EOS-S3 to SDF |
xiretza
|
2022-05-15 07:08 (UTC) |
|
rapidwright
|
2023.1.2_beta-1 |
0 |
0.00
|
Build Customized FPGA Implementations for Vivado |
xiretza
|
2023-08-23 09:39 (UTC) |
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rapidyaml-git
|
0.5.0.r14.g6a5a07f-1 |
2 |
0.00
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2023-05-14 13:45 (UTC) |
|
riscv64-unknown-elf-picolibc
|
1.8.5-1 |
0 |
0.00
|
Fork of newlib with stdio bits from avrlibc |
xiretza
|
2023-10-01 17:41 (UTC) |
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sdrangel-git
|
7.15.3.r0.028a44ce4-1 |
14 |
0.01
|
Qt5/OpenGL SDR and signal analyzer frontend. |
xiretza
|
2023-08-23 10:10 (UTC) |