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authorgraysky2022-12-04 04:54:54 -0500
committergraysky2022-12-04 04:54:54 -0500
commitb7be7481d7aa87ad993ccb664308ad9ee050e36d (patch)
tree5ae29d47df44eb10d5f69f71740cb89daaf82357 /0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch
parent07e04c3095da316777c5340a444d002dd255c6f4 (diff)
downloadaur-b7be7481d7aa87ad993ccb664308ad9ee050e36d.tar.gz
Update to 6.0.11-1
Diffstat (limited to '0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch')
-rw-r--r--0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch41
1 files changed, 41 insertions, 0 deletions
diff --git a/0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch b/0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch
new file mode 100644
index 000000000000..e8eff5c9f59d
--- /dev/null
+++ b/0004-drm-amdgpu-use-DRM_SCHED_FENCE_DONT_PIPELINE-for-VM-.patch
@@ -0,0 +1,41 @@
+From 80d7a84de8dde6b960af432751bde998b70acc98 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 7 Oct 2022 10:59:58 +0200
+Subject: [PATCH 4/6] drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM
+ updates
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Make sure that we always have a CPU round trip to let the submission
+code correctly decide if a TLB flush is necessary or not.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+index 718db7d98e5a..25ad3c7fa24b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+@@ -115,8 +115,15 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
+ amdgpu_bo_fence(p->vm->root.bo, f, true);
+ }
+
+- if (fence && !p->immediate)
++ if (fence && !p->immediate) {
++ /*
++ * Most hw generations now have a separate queue for page table
++ * updates, but when the queue is shared with userspace we need
++ * the extra CPU round trip to correctly flush the TLB.
++ */
++ set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
+ swap(*fence, f);
++ }
+ dma_fence_put(f);
+ return 0;
+
+--
+2.38.1
+