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| author | Cayetano Santos | 2020-03-16 23:20:29 +0100 |
|---|---|---|
| committer | Cayetano Santos | 2020-03-16 23:20:29 +0100 |
| commit | 2006eeb20bb5d6a7564e1f3ec5c66b7437e7b770 (patch) | |
| tree | 63426dfff027da4c4fe5fb132c112be8b2167a51 | |
| parent | 705199ade796951453d7b8269da7f397f52badf8 (diff) | |
| download | aur-2006eeb20bb5d6a7564e1f3ec5c66b7437e7b770.tar.gz | |
Updates to 1.3.1
| -rw-r--r-- | PKGBUILD | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1,7 +1,7 @@ # Maintainer: mox <demox@lavabit.com> pkgname=cocotb pkgver=1.3 -pkgrel=0 +pkgrel=1 epoch=0 pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" arch=('x86_64') # Can probably support other architectures as well, try your luck? @@ -16,7 +16,7 @@ optdepends=('iverilog: for simulating verilog designs' install=${pkgname}.install source=("https://github.com/cocotb/$pkgname/archive/v$pkgver.$pkgrel.tar.gz") -md5sums=('4db3d270943da293cf4dd7ce22594307') +md5sums=('0d9dd62350649c91c9a4fa202ad20dda') package() { cd "${srcdir}/cocotb-$pkgver.$pkgrel" |