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authorCayetano Santos2021-06-02 11:46:51 +0200
committerCayetano Santos2021-06-02 11:46:51 +0200
commit453d845c4cedcd02fc5f3346cfd7d499af0773cf (patch)
tree9fef7adb9d3a69f89045098ebc0f37c812f3165d
parentcc6379658fc2c2c2195d183fbad2c9942b3c3429 (diff)
downloadaur-453d845c4cedcd02fc5f3346cfd7d499af0773cf.tar.gz
Fix pkgver / pkgrel
-rw-r--r--.SRCINFO4
-rw-r--r--PKGBUILD6
2 files changed, 5 insertions, 5 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 3e6d73c26896..5e6ae85f6ae0 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,7 +1,7 @@
pkgbase = python-cocotb
pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
- pkgver = 1.5
- pkgrel = 2
+ pkgver = 1.5.2
+ pkgrel = 1
url = http://github.com/cocotb/cocotb/
arch = any
license = BSD
diff --git a/PKGBUILD b/PKGBUILD
index ad764ba249f2..4bb5847dc028 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -1,7 +1,7 @@
# Maintainer: csantosb <csantosb dot inventati dot org>
pkgname=python-cocotb
-pkgver=1.5
-pkgrel=2
+pkgver=1.5.2
+pkgrel=1
pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python"
arch=('any')
url="http://github.com/cocotb/cocotb/"
@@ -13,7 +13,7 @@ optdepends=('iverilog: for simulating verilog designs'
'gtkwave: for visualizing waveforms')
options=(!emptydirs)
-source=("git+https://github.com/cocotb/cocotb#tag=v${pkgver}.${pkgrel}")
+source=("git+https://github.com/cocotb/cocotb#tag=v${pkgver}")
md5sums=('SKIP')
build() {