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author | Cayetano Santos | 2020-03-08 12:40:40 +0100 |
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committer | Cayetano Santos | 2020-03-08 12:40:40 +0100 |
commit | 859be458253173030d4888628a3e70a16e371227 (patch) | |
tree | 98fd20bd0d4ac0ffdcfb240dce8b51171cd7a587 | |
parent | 685b15e4e8ab1e6f38f8edeb0aa73b1fa29d1f11 (diff) | |
download | aur-859be458253173030d4888628a3e70a16e371227.tar.gz |
Update srcinfo accordingly
-rw-r--r-- | .SRCINFO | 12 |
1 files changed, 5 insertions, 7 deletions
@@ -1,19 +1,17 @@ pkgbase = cocotb pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - pkgver = 1.1 - pkgrel = 1 + pkgver = 1.3 + pkgrel = 0 epoch = 0 - url = http://potential.ventures/cocotb/ + url = http://github.com/cocotb/ install = cocotb.install arch = x86_64 license = BSD makedepends = git depends = python - depends = swig optdepends = iverilog: for simulating verilog designs optdepends = ghdl: for simulating VHDL designs - source = https://github.com/potentialventures/cocotb/archive/v1.1.tar.gz - md5sums = 94483fb042f9b645acecdfab20d460a4 + source = https://github.com/cocotb/cocotb/archive/v1.3.0.tar.gz + md5sums = 4db3d270943da293cf4dd7ce22594307 pkgname = cocotb - |