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| author | Cayetano Santos | 2022-11-20 11:55:20 +0100 |
|---|---|---|
| committer | Cayetano Santos | 2022-11-20 11:55:20 +0100 |
| commit | ca7fc9b26a526c68385a5a32670f595f8a8db721 (patch) | |
| tree | a1dbe2eb9be9e9cbf5b954e5fab10e5e06fcf85e | |
| parent | 5bde74ca9eafa68cff308ab9c49791e54411378c (diff) | |
| download | aur-ca7fc9b26a526c68385a5a32670f595f8a8db721.tar.gz | |
version 1.7.2
| -rw-r--r-- | .SRCINFO | 4 | ||||
| -rw-r--r-- | PKGBUILD | 2 |
2 files changed, 3 insertions, 3 deletions
@@ -1,6 +1,6 @@ pkgbase = python-cocotb pkgdesc = Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python - pkgver = 1.7.0 + pkgver = 1.7.2 pkgrel = 1 url = http://github.com/cocotb/cocotb/ arch = any @@ -13,7 +13,7 @@ pkgbase = python-cocotb optdepends = ghdl: for simulating VHDL designs optdepends = gtkwave: for visualizing waveforms options = !emptydirs - source = git+https://github.com/cocotb/cocotb#tag=v1.7.0 + source = git+https://github.com/cocotb/cocotb#tag=v1.7.2 md5sums = SKIP pkgname = python-cocotb @@ -1,6 +1,6 @@ # Maintainer: csantosb <csantosb dot inventati dot org> pkgname=python-cocotb -pkgver=1.7.0 +pkgver=1.7.2 pkgrel=1 pkgdesc="Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python" arch=('any') |