Update to 5.7.4, rework i8042 patch

1 files changed, 156 insertions, 0 deletions

diff --git a/amdgpu-drm-next.patch b/amdgpu-drm-next.patch
new file mode 100644
index 000000000000..5898a9bfc650
--- /dev/null
+++ b/amdgpu-drm-next.patch
@@ -0,0 +1,156 @@
+diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
+index b73b10bce0df..e8e444eeb1cd 100644
+--- a/drivers/pci/p2pdma.c
++++ b/drivers/pci/p2pdma.c
+@@ -282,6 +282,8 @@ static const struct pci_p2pdma_whitelist_entry {
+ } pci_p2pdma_whitelist[] = {
+ 	/* AMD ZEN */
+ 	{PCI_VENDOR_ID_AMD,	0x1450,	0},
++	{PCI_VENDOR_ID_AMD,	0x15d0,	0},
++	{PCI_VENDOR_ID_AMD,	0x1630,	0},
+ 
+ 	/* Intel Xeon E5/Core i7 */
+ 	{PCI_VENDOR_ID_INTEL,	0x3c00, REQ_SAME_HOST_BRIDGE},
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 22943773ae31..6b94587df407 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -2856,8 +2856,8 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
+ 		/* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
+ 		data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
+ 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
+-
+-		pwr_10_0_gfxip_control_over_cgpg(adev, true);
++		if (adev->asic_type != CHIP_RENOIR)
++			pwr_10_0_gfxip_control_over_cgpg(adev, true);
+ 	}
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 623745b2d8b3..3e406eeeaff6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -415,7 +415,8 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
+ 	*value = 0;
+ 	for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
+ 		en = &soc15_allowed_read_registers[i];
+-		if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
++		if (adev->reg_offset[en->hwip][en->inst] &&
++			reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
+ 					+ en->reg_offset))
+ 			continue;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 33501c6c7189..899610fe2411 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -2202,6 +2202,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
+ 
+ 	switch (adev->asic_type) {
+ 	case CHIP_RAVEN:
++	case CHIP_RENOIR:
+ 		sdma_v4_1_update_power_gating(adev,
+ 				state == AMD_PG_STATE_GATE ? true : false);
+ 		break;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index a027a8f7b281..e036c868e354 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1742,8 +1742,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ 	case CHIP_RAVEN:
+ 	case CHIP_ARCTURUS:
+ 	case CHIP_RENOIR:
+-		if (adev->asic_type == CHIP_RAVEN ||
+-		    adev->asic_type == CHIP_RENOIR)
++		if (adev->flags & AMD_IS_APU)
+ 			adev->family = AMDGPU_FAMILY_RV;
+ 		else
+ 			adev->family = AMDGPU_FAMILY_AI;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 711e9dd19705..22943773ae31 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -1890,7 +1890,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ 			return r;
+ 	}
+ 
+-	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
++	if (adev->flags & AMD_IS_APU) {
+ 		/* TODO: double check the cp_table_size for RV */
+ 		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
+ 		r = amdgpu_gfx_rlc_init_cpt(adev);
+@@ -2384,7 +2384,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ 
+ 	gfx_v9_0_mec_fini(adev);
+ 	amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
+-	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
++	if (adev->flags & AMD_IS_APU) {
+ 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+ 				&adev->gfx.rlc.cp_table_gpu_addr,
+ 				(void **)&adev->gfx.rlc.cp_table_ptr);
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 899610fe2411..3278debe8cee 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -1774,7 +1774,7 @@ static int sdma_v4_0_early_init(void *handle)
+ 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ 	int r;
+ 
+-	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
++	if (adev->flags & AMD_IS_APU)
+ 		adev->sdma.num_instances = 1;
+ 	else if (adev->asic_type == CHIP_ARCTURUS)
+ 		adev->sdma.num_instances = 8;
+ 
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index c7c9e07962b9..623745b2d8b3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -670,14 +670,25 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+ 
+ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ {
++	int r;
++
+ 	/* Set IP register base before any HW register access */
+ 	switch (adev->asic_type) {
+ 	case CHIP_VEGA10:
+ 	case CHIP_VEGA12:
+ 	case CHIP_RAVEN:
+-	case CHIP_RENOIR:
+ 		vega10_reg_base_init(adev);
+ 		break;
++	case CHIP_RENOIR:
++		if (amdgpu_discovery) {
++			r = amdgpu_discovery_reg_base_init(adev);
++			if (r) {
++				DRM_WARN("failed to init reg base from ip discovery table, "
++					 "fallback to legacy init method\n");
++				vega10_reg_base_init(adev);
++			}
++		}
++		break;
+ 	case CHIP_VEGA20:
+ 		vega20_reg_base_init(adev);
+ 		break;
+ 		
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+index 0e638a77b5ee..babc966cdabd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+@@ -1709,12 +1709,8 @@ static int dcn21_populate_dml_pipes_from_context(
+ {
+ 	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
+ 	int i;
+-	struct resource_context *res_ctx = &context->res_ctx;
+ 
+-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+-
+-		if (!res_ctx->pipe_ctx[i].stream)
+-			continue;
++	for (i = 0; i < pipe_cnt; i++) {
+ 
+ 		pipes[i].pipe.src.hostvm = 1;
+ 		pipes[i].pipe.src.gpuvm = 1;