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authoregnappahz2021-06-26 15:17:32 +0200
committeregnappahz2021-06-26 15:17:32 +0200
commitf1083ea7eb36866419b8ea2567814bc0ffddaf72 (patch)
tree8c14c1cc944445281fb49ea887f7ff1891d5ce4b /idlebug.patch
parent304fbb632acd7c10f388aeee866b9a17503b88d4 (diff)
downloadaur-f1083ea7eb36866419b8ea2567814bc0ffddaf72.tar.gz
reverted doorbell commits for idlebug
Diffstat (limited to 'idlebug.patch')
-rw-r--r--idlebug.patch50
1 files changed, 50 insertions, 0 deletions
diff --git a/idlebug.patch b/idlebug.patch
new file mode 100644
index 00000000000..79794718bcf
--- /dev/null
+++ b/idlebug.patch
@@ -0,0 +1,50 @@
+From d71e282a6611b9e1742386a2a4764fb766bc970b Mon Sep 17 00:00:00 2001
+From: egnappahz <egnappah@gmail.com>
+Date: Thu, 24 Jun 2021 12:46:46 +0200
+Subject: [PATCH] Revert for sienna idle bug
+
+Signed-off-by: egnappahz <egnappah@gmail.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +-----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +-----
+ 2 files changed, 2 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+index 72d23651501d..2342c5d216f9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+@@ -6769,12 +6769,8 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 1fdfb7783404..d2c020a91c0b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3623,12 +3623,8 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
+ if (ring->use_doorbell) {
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
+ (adev->doorbell_index.kiq * 2) << 2);
+- /* If GC has entered CGPG, ringing doorbell > first page doesn't
+- * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+- * this issue.
+- */
+ WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+- (adev->doorbell.size - 4));
++ (adev->doorbell_index.userqueue_end * 2) << 2);
+ }
+
+ WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
+--
+2.32.0
+