diff options
Diffstat (limited to '0002-drm-i915-dp-Use-slow-and-wide-link-training-for-ever.patch')
| -rw-r--r-- | 0002-drm-i915-dp-Use-slow-and-wide-link-training-for-ever.patch | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/0002-drm-i915-dp-Use-slow-and-wide-link-training-for-ever.patch b/0002-drm-i915-dp-Use-slow-and-wide-link-training-for-ever.patch new file mode 100644 index 000000000000..f7e49d422e12 --- /dev/null +++ b/0002-drm-i915-dp-Use-slow-and-wide-link-training-for-ever.patch @@ -0,0 +1,117 @@ +From d290a24cb45e73e4f8d2700d5f47c2132d066fe2 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng <kai.heng.feng@canonical.com> +Date: Wed, 21 Apr 2021 13:20:31 +0800 +Subject: [PATCH 2/3] drm/i915/dp: Use slow and wide link training for + everything +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Screen flickers on Innolux eDP 1.3 panel when clock rate 540000 is in use. + +According to the panel vendor, though clock rate 540000 is advertised, +but the max clock rate it really supports is 270000. + +Ville Syrjälä mentioned that fast and narrow also breaks some eDP 1.4 +panel, so use slow and wide training for all panels to resolve the +issue. + +User also confirmed that the new strategy doesn't introduce any +regression on XPS 9380. + +v2: + - Use slow and wide for everything. + +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3384 +References: https://gitlab.freedesktop.org/drm/intel/-/issues/272 +Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> +Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +Link: https://patchwork.freedesktop.org/patch/msgid/20210421052054.1434718-1-kai.heng.feng@canonical.com +(cherry picked from commit acca7762eb71bc05a8f28d29320d193150051f79) +Fixes: 2bbd6dba84d4 ("drm/i915: Try to use fast+narrow link on eDP again and fall back to the old max strategy on failure") +Cc: <stable@vger.kernel.org> # v5.12+ +Signed-off-by: Jani Nikula <jani.nikula@intel.com> +--- + drivers/gpu/drm/i915/display/intel_dp.c | 59 +++---------------------- + 1 file changed, 5 insertions(+), 54 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 775d89b6c3fc..5a5103632564 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -1174,44 +1174,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, + return -EINVAL; + } + +-/* Optimize link config in order: max bpp, min lanes, min clock */ +-static int +-intel_dp_compute_link_config_fast(struct intel_dp *intel_dp, +- struct intel_crtc_state *pipe_config, +- const struct link_config_limits *limits) +-{ +- const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; +- int bpp, clock, lane_count; +- int mode_rate, link_clock, link_avail; +- +- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { +- int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); +- +- mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, +- output_bpp); +- +- for (lane_count = limits->min_lane_count; +- lane_count <= limits->max_lane_count; +- lane_count <<= 1) { +- for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { +- link_clock = intel_dp->common_rates[clock]; +- link_avail = intel_dp_max_data_rate(link_clock, +- lane_count); +- +- if (mode_rate <= link_avail) { +- pipe_config->lane_count = lane_count; +- pipe_config->pipe_bpp = bpp; +- pipe_config->port_clock = link_clock; +- +- return 0; +- } +- } +- } +- } +- +- return -EINVAL; +-} +- + static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) + { + int i, num_bpc; +@@ -1461,22 +1423,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, + intel_dp_can_bigjoiner(intel_dp)) + pipe_config->bigjoiner = true; + +- if (intel_dp_is_edp(intel_dp)) +- /* +- * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4 +- * section A.1: "It is recommended that the minimum number of +- * lanes be used, using the minimum link rate allowed for that +- * lane configuration." +- * +- * Note that we fall back to the max clock and lane count for eDP +- * panels that fail with the fast optimal settings (see +- * intel_dp->use_max_params), in which case the fast vs. wide +- * choice doesn't matter. +- */ +- ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits); +- else +- /* Optimize for slow and wide. */ +- ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); ++ /* ++ * Optimize for slow and wide for everything, because there are some ++ * eDP 1.3 and 1.4 panels don't work well with fast and narrow. ++ */ ++ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); +-- +2.31.1 + |