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-rw-r--r--0024-V8-0-4-PCI-vmd-Enable-PCIe-ASPM-and-LTR-on-select-hardware.patch1420
1 files changed, 1420 insertions, 0 deletions
diff --git a/0024-V8-0-4-PCI-vmd-Enable-PCIe-ASPM-and-LTR-on-select-hardware.patch b/0024-V8-0-4-PCI-vmd-Enable-PCIe-ASPM-and-LTR-on-select-hardware.patch
new file mode 100644
index 000000000000..b71f08daabeb
--- /dev/null
+++ b/0024-V8-0-4-PCI-vmd-Enable-PCIe-ASPM-and-LTR-on-select-hardware.patch
@@ -0,0 +1,1420 @@
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+From: "David E. Box" <david.e.box@linux.intel.com>
+To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com,
+ michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select hardware
+Date: Wed, 2 Nov 2022 19:18:18 -0700
+Message-Id: <20221103021822.308586-1-david.e.box@linux.intel.com>
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+List-ID: <linux-pci.vger.kernel.org>
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+
+This series adds a work around for enabling PCIe ASPM and for setting PCIe
+LTR values on VMD reserved root ports on select platforms. While
+configuration of these capabilities is usually done by BIOS, on these
+platforms these capabilities will not be configured because the ports are
+not visible to BIOS. This was part of an initial design that expected the
+driver to completely handle the ports, including power management. However
+on Linux those ports are still managed by the PCIe core, which has the
+expectation that they adhere to device standards including BIOS
+configuration, leading to this problem.
+
+The target platforms are Tiger Lake, Alder Lake, and Raptor Lake though the
+latter has already implemented support for configuring the LTR values.
+Meteor Lake is expected add BIOS ASPM support, eliminating the future need
+for this work around.
+
+Note, the driver programs the LTRs because BIOS would also normally do this
+for devices that do not set them by default. Without this, SoC power
+management would be blocked on those platform. This SoC specific value is
+the maximum latency required to allow the SoC to enter the deepest power
+state.
+
+This patch addresses the following open bugzillas on VMD enabled laptops
+that cannot enter low power states.
+
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=212355
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=215063
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=213717
+
+David E. Box (3):
+ PCI: vmd: Use PCI_VDEVICE in device list
+ PCI: vmd: Create feature grouping for client products
+ PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+
+Michael Bottini (1):
+ PCI/ASPM: Add pci_enable_link_state()
+
+ drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++----------
+ drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++
+ include/linux/pci.h | 7 +++
+ 3 files changed, 131 insertions(+), 26 deletions(-)
+
+
+base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
+--
+2.25.1
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+From: "David E. Box" <david.e.box@linux.intel.com>
+To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com,
+ michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH V8 1/4] PCI/ASPM: Add pci_enable_link_state()
+Date: Wed, 2 Nov 2022 19:18:19 -0700
+Message-Id: <20221103021822.308586-2-david.e.box@linux.intel.com>
+X-Mailer: git-send-email 2.25.1
+In-Reply-To: <20221103021822.308586-1-david.e.box@linux.intel.com>
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
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+List-ID: <linux-pci.vger.kernel.org>
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+
+From: Michael Bottini <michael.a.bottini@linux.intel.com>
+
+Add pci_enable_link_state() to allow devices to change the default BIOS
+configured states. Clears the BIOS default settings then sets the new
+states and reconfigures the link under the semaphore. Also add
+PCIE_LINK_STATE_ALL macro for convenience for callers that want to enable
+all link states.
+
+Signed-off-by: Michael Bottini <michael.a.bottini@linux.intel.com>
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ V8
+ - No change
+
+ V7
+ - Fix description as suggested by Bjorn
+ - Rename function to pci_enable_link_state
+
+ V6
+ - No change
+ V5
+ - Rename to pci_enable_default_link_state and model after
+ pci_disable_link_state() as suggested by Bjorn.
+ - Add helper PCIE_LINK_STATE_ALL which sets bits for all links states and
+ clock pm.
+ - Clarify commit language to indicate the function changes the default
+ link states (not ASPM policy).
+ V4
+ - Refactor vmd_enable_apsm() to exit early, making the lines shorter
+ and more readable. Suggested by Christoph.
+ V3
+ - No changes
+ V2
+ - Use return status to print pci_info message if ASPM cannot be enabled.
+ - Add missing static declaration, caught by lkp@intel.com
+
+ drivers/pci/pcie/aspm.c | 54 +++++++++++++++++++++++++++++++++++++++++
+ include/linux/pci.h | 7 ++++++
+ 2 files changed, 61 insertions(+)
+
+diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
+index 53a1fa306e1e..339c686a5094 100644
+--- a/drivers/pci/pcie/aspm.c
++++ b/drivers/pci/pcie/aspm.c
+@@ -1181,6 +1181,60 @@ int pci_disable_link_state(struct pci_dev *pdev, int state)
+ }
+ EXPORT_SYMBOL(pci_disable_link_state);
+
++/**
++ * pci_enable_link_state - Clear and set the default device link state so that
++ * the link may be allowed to enter the specified states. Note that if the
++ * BIOS didn't grant ASPM control to the OS, this does nothing because we can't
++ * touch the LNKCTL register. Also note that this does not enable states
++ * disabled by pci_disable_link_state(). Return 0 or a negative errno.
++ *
++ * @pdev: PCI device
++ * @state: Mask of ASPM link states to enable
++ */
++int pci_enable_link_state(struct pci_dev *pdev, int state)
++{
++ struct pcie_link_state *link = pcie_aspm_get_link(pdev);
++
++ if (!link)
++ return -EINVAL;
++ /*
++ * A driver requested that ASPM be enabled on this device, but
++ * if we don't have permission to manage ASPM (e.g., on ACPI
++ * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
++ * the _OSC method), we can't honor that request.
++ */
++ if (aspm_disabled) {
++ pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n");
++ return -EPERM;
++ }
++
++ down_read(&pci_bus_sem);
++ mutex_lock(&aspm_lock);
++ link->aspm_default = 0;
++ if (state & PCIE_LINK_STATE_L0S)
++ link->aspm_default |= ASPM_STATE_L0S;
++ if (state & PCIE_LINK_STATE_L1)
++ /* L1 PM substates require L1 */
++ link->aspm_default |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
++ if (state & PCIE_LINK_STATE_L1_1)
++ link->aspm_default |= ASPM_STATE_L1_1;
++ if (state & PCIE_LINK_STATE_L1_2)
++ link->aspm_default |= ASPM_STATE_L1_2;
++ if (state & PCIE_LINK_STATE_L1_1_PCIPM)
++ link->aspm_default |= ASPM_STATE_L1_1_PCIPM;
++ if (state & PCIE_LINK_STATE_L1_2_PCIPM)
++ link->aspm_default |= ASPM_STATE_L1_2_PCIPM;
++ pcie_config_aspm_link(link, policy_to_aspm_state(link));
++
++ link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0;
++ pcie_set_clkpm(link, policy_to_clkpm_state(link));
++ mutex_unlock(&aspm_lock);
++ up_read(&pci_bus_sem);
++
++ return 0;
++}
++EXPORT_SYMBOL(pci_enable_link_state);
++
+ static int pcie_aspm_set_policy(const char *val,
+ const struct kernel_param *kp)
+ {
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 2bda4a4e47e8..8c35f15e6012 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -1651,10 +1651,15 @@ extern bool pcie_ports_native;
+ #define PCIE_LINK_STATE_L1_2 BIT(4)
+ #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
+ #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
++#define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |\
++ PCIE_LINK_STATE_CLKPM | PCIE_LINK_STATE_L1_1 |\
++ PCIE_LINK_STATE_L1_2 | PCIE_LINK_STATE_L1_1_PCIPM |\
++ PCIE_LINK_STATE_L1_2_PCIPM)
+
+ #ifdef CONFIG_PCIEASPM
+ int pci_disable_link_state(struct pci_dev *pdev, int state);
+ int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
++int pci_enable_link_state(struct pci_dev *pdev, int state);
+ void pcie_no_aspm(void);
+ bool pcie_aspm_support_enabled(void);
+ bool pcie_aspm_enabled(struct pci_dev *pdev);
+@@ -1663,6 +1668,8 @@ static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
+ { return 0; }
+ static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
+ { return 0; }
++static inline int pci_enable_link_state(struct pci_dev *pdev, int state)
++{ return 0; }
+ static inline void pcie_no_aspm(void) { }
+ static inline bool pcie_aspm_support_enabled(void) { return false; }
+ static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
+--
+2.25.1
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+From: "David E. Box" <david.e.box@linux.intel.com>
+To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com,
+ michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH V8 2/4] PCI: vmd: Use PCI_VDEVICE in device list
+Date: Wed, 2 Nov 2022 19:18:20 -0700
+Message-Id: <20221103021822.308586-3-david.e.box@linux.intel.com>
+X-Mailer: git-send-email 2.25.1
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+List-ID: <linux-pci.vger.kernel.org>
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+
+Refactor the PCI ID list to use PCI_VDEVICE.
+
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Reviewed-by: Jon Derrick <jonathan.derrick@linux.dev>
+Reviewed-by: Nirmal Patel <nirmal.patel@linux.intel.com>
+---
+ V8 - No change
+
+ V7 - New Patch. Separate patch suggested by Lorenzo
+
+ drivers/pci/controller/vmd.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
+index e06e9f4fc50f..9dedca714c18 100644
+--- a/drivers/pci/controller/vmd.c
++++ b/drivers/pci/controller/vmd.c
+@@ -994,33 +994,33 @@ static int vmd_resume(struct device *dev)
+ static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
+
+ static const struct pci_device_id vmd_ids[] = {
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
++ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
++ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_CAN_BYPASS_MSI_REMAP,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f),
++ {PCI_VDEVICE(INTEL, 0x467f),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d),
++ {PCI_VDEVICE(INTEL, 0x4c3d),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa77f),
++ {PCI_VDEVICE(INTEL, 0xa77f),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7d0b),
++ {PCI_VDEVICE(INTEL, 0x7d0b),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xad0b),
++ {PCI_VDEVICE(INTEL, 0xad0b),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+- {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
++ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
+ .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_OFFSET_FIRST_VECTOR,},
+--
+2.25.1
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
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+ by linux.intel.com (Postfix) with ESMTP id 56E3E580B9E;
+ Wed, 2 Nov 2022 19:18:23 -0700 (PDT)
+From: "David E. Box" <david.e.box@linux.intel.com>
+To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com,
+ michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH V8 3/4] PCI: vmd: Create feature grouping for client products
+Date: Wed, 2 Nov 2022 19:18:21 -0700
+Message-Id: <20221103021822.308586-4-david.e.box@linux.intel.com>
+X-Mailer: git-send-email 2.25.1
+In-Reply-To: <20221103021822.308586-1-david.e.box@linux.intel.com>
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
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+List-ID: <linux-pci.vger.kernel.org>
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+
+Simplify the device ID list by creating a grouping of features shared by
+client products.
+
+Suggested-by: Jon Derrick <jonathan.derrick@linux.dev>
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+---
+
+ V8 - New patch.
+
+ drivers/pci/controller/vmd.c | 28 ++++++++++------------------
+ 1 file changed, 10 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
+index 9dedca714c18..86f3085db014 100644
+--- a/drivers/pci/controller/vmd.c
++++ b/drivers/pci/controller/vmd.c
+@@ -68,6 +68,10 @@ enum vmd_features {
+ VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4),
+ };
+
++#define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \
++ VMD_FEAT_HAS_BUS_RESTRICTIONS | \
++ VMD_FEAT_OFFSET_FIRST_VECTOR)
++
+ static DEFINE_IDA(vmd_instance_ida);
+
+ /*
+@@ -1001,29 +1005,17 @@ static const struct pci_device_id vmd_ids[] = {
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_CAN_BYPASS_MSI_REMAP,},
+ {PCI_VDEVICE(INTEL, 0x467f),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {PCI_VDEVICE(INTEL, 0x4c3d),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {PCI_VDEVICE(INTEL, 0xa77f),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {PCI_VDEVICE(INTEL, 0x7d0b),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {PCI_VDEVICE(INTEL, 0xad0b),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
+- .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
+- VMD_FEAT_HAS_BUS_RESTRICTIONS |
+- VMD_FEAT_OFFSET_FIRST_VECTOR,},
++ .driver_data = VMD_FEATS_CLIENT,},
+ {0,}
+ };
+ MODULE_DEVICE_TABLE(pci, vmd_ids);
+--
+2.25.1
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+From: "David E. Box" <david.e.box@linux.intel.com>
+To: nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, david.e.box@linux.intel.com,
+ michael.a.bottini@intel.com, rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Subject: [PATCH V8 4/4] PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+Date: Wed, 2 Nov 2022 19:18:22 -0700
+Message-Id: <20221103021822.308586-5-david.e.box@linux.intel.com>
+X-Mailer: git-send-email 2.25.1
+In-Reply-To: <20221103021822.308586-1-david.e.box@linux.intel.com>
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
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+List-ID: <linux-pci.vger.kernel.org>
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+
+PCIe ports reserved for VMD use are not visible to BIOS and therefore not
+configured to enable PCIe ASPM or LTR values (which BIOS will configure if
+they are not set). Lack of this programming results in high power
+consumption on laptops as reported in bugzilla. For affected products use
+pci_enable_link_state to set the allowed link states for devices on the
+root ports. Also set the LTR value to the maximum value needed for the SoC.
+
+This is a workaround for products from Rocket Lake through Alder Lake.
+Raptor Lake, the latest product at this time, has already implemented LTR
+configuring in BIOS. Future products will move ASPM configuration back to
+BIOS as well. As this solution is intended for laptops, support is not
+added for hotplug or for devices downstream of a switch on the root port.
+
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=212355
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=215063
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=213717
+
+Signed-off-by: Michael Bottini <michael.a.bottini@linux.intel.com>
+Signed-off-by: David E. Box <david.e.box@linux.intel.com>
+Reviewed-by: Jon Derrick <jonathan.derrick@linux.dev>
+Reviewed-by: Nirmal Patel <nirmal.patel@linux.intel.com>
+---
+ V8
+ - Removed struct vmd_device_data patch. Instead use #define for the LTR
+ value which is the same across all products needing the quirk.
+ V7
+ - No change
+ V6
+ - Set ASPM first before setting LTR. This is needed because some
+ devices may only have LTR set by BIOS and not ASPM
+ - Skip setting the LTR if the current LTR in non-zero.
+ V5
+ - Provide the LTR value as driver data.
+ - Use DWORD for the config space write to avoid PCI WORD access bug.
+ - Set ASPM links firsts, enabling all link states, before setting a
+ default LTR if the capability is present
+ - Add kernel message that VMD is setting the device LTR.
+ V4
+ - Refactor vmd_enable_apsm() to exit early, making the lines shorter
+ and more readable. Suggested by Christoph.
+ V3
+ - No changes
+ V2
+ - Use return status to print pci_info message if ASPM cannot be enabled.
+ - Add missing static declaration, caught by lkp@intel.com
+ drivers/pci/controller/vmd.c | 64 ++++++++++++++++++++++++++++++++----
+ 1 file changed, 58 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
+index 86f3085db014..cba57e3091f6 100644
+--- a/drivers/pci/controller/vmd.c
++++ b/drivers/pci/controller/vmd.c
+@@ -66,12 +66,22 @@ enum vmd_features {
+ * interrupt handling.
+ */
+ VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4),
++
++ /*
++ * Enable ASPM on the PCIE root ports and set the default LTR of the
++ * storage devices on platforms where these values are not configured by
++ * BIOS. This is needed for laptops, which require these settings for
++ * proper power management of the SoC.
++ */
++ VMD_FEAT_BIOS_PM_QUIRK = (1 << 5),
+ };
+
+ #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \
+ VMD_FEAT_HAS_BUS_RESTRICTIONS | \
+ VMD_FEAT_OFFSET_FIRST_VECTOR)
+
++#define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */
++
+ static DEFINE_IDA(vmd_instance_ida);
+
+ /*
+@@ -713,6 +723,46 @@ static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge,
+ vmd_bridge->native_dpc = root_bridge->native_dpc;
+ }
+
++/*
++ * Enable ASPM and LTR settings on devices that aren't configured by BIOS.
++ */
++static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata)
++{
++ unsigned long features = *(unsigned long *)userdata;
++ u16 ltr = VMD_BIOS_PM_QUIRK_LTR;
++ u32 ltr_reg;
++ int pos;
++
++ if (!(features & VMD_FEAT_BIOS_PM_QUIRK))
++ return 0;
++
++ pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL);
++
++ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR);
++ if (!pos)
++ return 0;
++
++ /*
++ * Skip if the max snoop LTR is non-zero, indicating BIOS has set it
++ * so the LTR quirk is not needed.
++ */
++ pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, &ltr_reg);
++ if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK)))
++ return 0;
++
++ /*
++ * Set the default values to the maximum required by the platform to
++ * allow the deepest power management savings. Write as a DWORD where
++ * the lower word is the max snoop latency and the upper word is the
++ * max non-snoop latency.
++ */
++ ltr_reg = (ltr << 16) | ltr;
++ pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg);
++ pci_info(pdev, "VMD: Default LTR value set by driver\n");
++
++ return 0;
++}
++
+ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
+ {
+ struct pci_sysdata *sd = &vmd->sysdata;
+@@ -867,6 +917,8 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
+ pci_reset_bus(child->self);
+ pci_assign_unassigned_bus_resources(vmd->bus);
+
++ pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features);
++
+ /*
+ * VMD root buses are virtual and don't return true on pci_is_pcie()
+ * and will fail pcie_bus_configure_settings() early. It can instead be
+@@ -1005,17 +1057,17 @@ static const struct pci_device_id vmd_ids[] = {
+ VMD_FEAT_HAS_BUS_RESTRICTIONS |
+ VMD_FEAT_CAN_BYPASS_MSI_REMAP,},
+ {PCI_VDEVICE(INTEL, 0x467f),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {PCI_VDEVICE(INTEL, 0x4c3d),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {PCI_VDEVICE(INTEL, 0xa77f),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {PCI_VDEVICE(INTEL, 0x7d0b),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {PCI_VDEVICE(INTEL, 0xad0b),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
+- .driver_data = VMD_FEATS_CLIENT,},
++ .driver_data = VMD_FEATS_CLIENT | VMD_FEAT_BIOS_PM_QUIRK,},
+ {0,}
+ };
+ MODULE_DEVICE_TABLE(pci, vmd_ids);
+--
+2.25.1
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+Message-ID: <5c766840-e092-45ea-0664-7bbdb78b933a@canonical.com>
+Date: Wed, 23 Nov 2022 18:27:18 +0800
+MIME-Version: 1.0
+User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101
+ Thunderbird/102.5.0
+Subject: Re: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select
+ hardware
+Content-Language: en-US
+To: "David E. Box" <david.e.box@linux.intel.com>
+Cc: michael.a.bottini@intel.com, linux-pci@vger.kernel.org,
+ linux-kernel@vger.kernel.org, me@adhityamohan.in,
+ rafael@kernel.org, hch@infradead.org, robh@kernel.org,
+ bhelgaas@google.com, kw@linux.com, lorenzo.pieralisi@arm.com,
+ nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
+From: You-Sheng Yang <vicamo.yang@canonical.com>
+In-Reply-To: <20221103021822.308586-1-david.e.box@linux.intel.com>
+Content-Type: text/plain; charset=UTF-8; format=flowed
+Content-Transfer-Encoding: 8bit
+Precedence: bulk
+List-ID: <linux-pci.vger.kernel.org>
+X-Mailing-List: linux-pci@vger.kernel.org
+
+Hi David,
+
+On 11/3/22 10:18, David E. Box wrote:
+> This series adds a work around for enabling PCIe ASPM and for setting PCIe
+> LTR values on VMD reserved root ports on select platforms. While
+> configuration of these capabilities is usually done by BIOS, on these
+> platforms these capabilities will not be configured because the ports are
+> not visible to BIOS. This was part of an initial design that expected the
+> driver to completely handle the ports, including power management. However
+> on Linux those ports are still managed by the PCIe core, which has the
+> expectation that they adhere to device standards including BIOS
+> configuration, leading to this problem.
+>
+> The target platforms are Tiger Lake, Alder Lake, and Raptor Lake though the
+> latter has already implemented support for configuring the LTR values.
+> Meteor Lake is expected add BIOS ASPM support, eliminating the future need
+> for this work around.
+
+
+It appears to me that this patch series works only on Tiger Lake. We
+have tried to revert our current work-arounds in Ubuntu kernels
+generic-5.15/oem-5.17/oem-6.0/unstable-6.1 and apply this series, the
+prebuilt kernels can be found in:
+
+   https://launchpad.net/~vicamo/+archive/ubuntu/ppa-1996620
+
+However, only TGL can still enter PC10 as before.
+
+
+ADL-M, RPL platforms will stay in PC3 with vmd LTR set, but ASPM
+disabled. i915 RC6 blocked, too:
+
+$ sudo cat /sys/kernel/debug/dri/
+
+0/i915_dmc_info
+...
+DC3CO count: 0
+DC3 -> DC5 count: 100
+DC5 -> DC6 count: 0
+
+
+> Note, the driver programs the LTRs because BIOS would also normally do this
+> for devices that do not set them by default. Without this, SoC power
+> management would be blocked on those platform. This SoC specific value is
+> the maximum latency required to allow the SoC to enter the deepest power
+> state.
+>
+> This patch addresses the following open bugzillas on VMD enabled laptops
+> that cannot enter low power states.
+>
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=212355
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=215063
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=213717
+>
+> David E. Box (3):
+> PCI: vmd: Use PCI_VDEVICE in device list
+> PCI: vmd: Create feature grouping for client products
+> PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+>
+> Michael Bottini (1):
+> PCI/ASPM: Add pci_enable_link_state()
+>
+> drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++----------
+> drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++
+> include/linux/pci.h | 7 +++
+> 3 files changed, 131 insertions(+), 26 deletions(-)
+>
+>
+> base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
+
+
+Regards,
+You-Sheng Yang
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+Message-ID: <17b05a72d2db1074cef9d5e9f85b347850f171d5.camel@linux.intel.com>
+Subject: Re: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select
+ hardware
+From: "David E. Box" <david.e.box@linux.intel.com>
+Reply-To: david.e.box@linux.intel.com
+To: You-Sheng Yang <vicamo.yang@canonical.com>
+Cc: michael.a.bottini@intel.com, linux-pci@vger.kernel.org,
+ linux-kernel@vger.kernel.org, me@adhityamohan.in,
+ rafael@kernel.org, hch@infradead.org, robh@kernel.org,
+ bhelgaas@google.com, kw@linux.com, lorenzo.pieralisi@arm.com,
+ nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev
+Date: Wed, 23 Nov 2022 08:09:48 -0800
+In-Reply-To: <5c766840-e092-45ea-0664-7bbdb78b933a@canonical.com>
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
+ <5c766840-e092-45ea-0664-7bbdb78b933a@canonical.com>
+Organization: David E. Box
+Content-Type: text/plain; charset="UTF-8"
+Content-Transfer-Encoding: quoted-printable
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+MIME-Version: 1.0
+Precedence: bulk
+List-ID: <linux-pci.vger.kernel.org>
+X-Mailing-List: linux-pci@vger.kernel.org
+
+Hi You-Sheng,
+
+On Wed, 2022-11-23 at 18:27 +0800, You-Sheng Yang wrote:
+> Hi David,
+>=20
+> On 11/3/22 10:18, David E. Box wrote:
+> > This series adds a work around for enabling PCIe ASPM and for setting P=
+CIe
+> > LTR values on VMD reserved root ports on select platforms. While
+> > configuration of these capabilities is usually done by BIOS, on these
+> > platforms these capabilities will not be configured because the ports a=
+re
+> > not visible to BIOS. This was part of an initial design that expected t=
+he
+> > driver to completely handle the ports, including power management. Howe=
+ver
+> > on Linux those ports are still managed by the PCIe core, which has the
+> > expectation that they adhere to device standards including BIOS
+> > configuration, leading to this problem.
+> >=20
+> > The target platforms are Tiger Lake, Alder Lake, and Raptor Lake though=
+ the
+> > latter has already implemented support for configuring the LTR values.
+> > Meteor Lake is expected add BIOS ASPM support, eliminating the future n=
+eed
+> > for this work around.
+>=20
+>=20
+> It appears to me that this patch series works only on Tiger Lake. We=20
+> have tried to revert our current work-arounds in Ubuntu kernels=20
+> generic-5.15/oem-5.17/oem-6.0/unstable-6.1 and apply this series, the=20
+> prebuilt kernels can be found in:
+>=20
+> =C2=A0=C2=A0 https://launchpad.net/~vicamo/+archive/ubuntu/ppa-1996620
+>=20
+> However, only TGL can still enter PC10 as before.
+>=20
+>=20
+> ADL-M, RPL platforms will stay in PC3 with vmd LTR set, but ASPM=20
+> disabled.
+
+For the patch to work BIOS must allow the OS to control ASPM. If this is no=
+t the
+case then you will see the message "ACPI FADT declares the system doesn't
+support PCIe ASPM, so disable it". Please check for this on the systems tha=
+t
+don't work. If so the only option is a BIOS change to enable it.
+
+David
+
+> i915 RC6 blocked, too:
+>=20
+> $ sudo cat /sys/kernel/debug/dri/
+>=20
+> 0/i915_dmc_info
+> ...
+> DC3CO count: 0
+> DC3 -> DC5 count: 100
+> DC5 -> DC6 count: 0
+>=20
+>=20
+> > Note, the driver programs the LTRs because BIOS would also normally do =
+this
+> > for devices that do not set them by default. Without this, SoC power
+> > management would be blocked on those platform. This SoC specific value =
+is
+> > the maximum latency required to allow the SoC to enter the deepest powe=
+r
+> > state.
+> >=20
+> > This patch addresses the following open bugzillas on VMD enabled laptop=
+s
+> > that cannot enter low power states.
+> >=20
+> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D212355
+> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D215063
+> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D213717
+> >=20
+> > David E. Box (3):
+> > =C2=A0=C2=A0 PCI: vmd: Use PCI_VDEVICE in device list
+> > =C2=A0=C2=A0 PCI: vmd: Create feature grouping for client products
+> > =C2=A0=C2=A0 PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+> >=20
+> > Michael Bottini (1):
+> > =C2=A0=C2=A0 PCI/ASPM: Add pci_enable_link_state()
+> >=20
+> > =C2=A0 drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++----=
+------
+> > =C2=A0 drivers/pci/pcie/aspm.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 54 +++++=
++++++++++++++++
+> > =C2=A0 include/linux/pci.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
+=A0=C2=A0 |=C2=A0 7 +++
+> > =C2=A0 3 files changed, 131 insertions(+), 26 deletions(-)
+> >=20
+> >=20
+> > base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
+>=20
+>=20
+> Regards,
+> You-Sheng Yang
+>=20
+
+
+From mboxrd@z Thu Jan 1 00:00:00 1970
+Return-Path: <linux-pci-owner@kernel.org>
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+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
+ <5c766840-e092-45ea-0664-7bbdb78b933a@canonical.com> <17b05a72d2db1074cef9d5e9f85b347850f171d5.camel@linux.intel.com>
+In-Reply-To: <17b05a72d2db1074cef9d5e9f85b347850f171d5.camel@linux.intel.com>
+From: You-Sheng Yang <vicamo.yang@canonical.com>
+Date: Fri, 25 Nov 2022 00:39:58 +0800
+Message-ID: <CA+rHWA+7KudasAMnO=dCUSQWb76Eu=DALA=1eLd_jjLw0dEMkA@mail.gmail.com>
+Subject: Re: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select hardware
+To: david.e.box@linux.intel.com
+Cc: michael.a.bottini@intel.com, linux-pci@vger.kernel.org,
+ linux-kernel@vger.kernel.org, me@adhityamohan.in,
+ rafael@kernel.org, hch@infradead.org, robh@kernel.org,
+ bhelgaas@google.com, kw@linux.com, lorenzo.pieralisi@arm.com,
+ nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev
+Content-Type: text/plain; charset="UTF-8"
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+
+On Thu, Nov 24, 2022 at 12:09 AM David E. Box
+<david.e.box@linux.intel.com> wrote:
+>
+> Hi You-Sheng,
+>
+> On Wed, 2022-11-23 at 18:27 +0800, You-Sheng Yang wrote:
+> > Hi David,
+> >
+> > On 11/3/22 10:18, David E. Box wrote:
+> > > This series adds a work around for enabling PCIe ASPM and for setting PCIe
+> > > LTR values on VMD reserved root ports on select platforms. While
+> > > configuration of these capabilities is usually done by BIOS, on these
+> > > platforms these capabilities will not be configured because the ports are
+> > > not visible to BIOS. This was part of an initial design that expected the
+> > > driver to completely handle the ports, including power management. However
+> > > on Linux those ports are still managed by the PCIe core, which has the
+> > > expectation that they adhere to device standards including BIOS
+> > > configuration, leading to this problem.
+> > >
+> > > The target platforms are Tiger Lake, Alder Lake, and Raptor Lake though the
+> > > latter has already implemented support for configuring the LTR values.
+> > > Meteor Lake is expected add BIOS ASPM support, eliminating the future need
+> > > for this work around.
+> >
+> >
+> > It appears to me that this patch series works only on Tiger Lake. We
+> > have tried to revert our current work-arounds in Ubuntu kernels
+> > generic-5.15/oem-5.17/oem-6.0/unstable-6.1 and apply this series, the
+> > prebuilt kernels can be found in:
+> >
+> > https://launchpad.net/~vicamo/+archive/ubuntu/ppa-1996620
+> >
+> > However, only TGL can still enter PC10 as before.
+> >
+> >
+> > ADL-M, RPL platforms will stay in PC3 with vmd LTR set, but ASPM
+> > disabled.
+>
+> For the patch to work BIOS must allow the OS to control ASPM. If this is not the
+> case then you will see the message "ACPI FADT declares the system doesn't
+> support PCIe ASPM, so disable it". Please check for this on the systems that
+> don't work. If so the only option is a BIOS change to enable it.
+
+Thank you. It's exactly what you said. The ADL-M/RPL platforms I have
+do not support OS PCIe ASPM.
+
+> David
+>
+> > i915 RC6 blocked, too:
+> >
+> > $ sudo cat /sys/kernel/debug/dri/
+> >
+> > 0/i915_dmc_info
+> > ...
+> > DC3CO count: 0
+> > DC3 -> DC5 count: 100
+> > DC5 -> DC6 count: 0
+> >
+> >
+> > > Note, the driver programs the LTRs because BIOS would also normally do this
+> > > for devices that do not set them by default. Without this, SoC power
+> > > management would be blocked on those platform. This SoC specific value is
+> > > the maximum latency required to allow the SoC to enter the deepest power
+> > > state.
+> > >
+> > > This patch addresses the following open bugzillas on VMD enabled laptops
+> > > that cannot enter low power states.
+> > >
+> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=212355
+> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=215063
+> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=213717
+> > >
+> > > David E. Box (3):
+> > > PCI: vmd: Use PCI_VDEVICE in device list
+> > > PCI: vmd: Create feature grouping for client products
+> > > PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+> > >
+> > > Michael Bottini (1):
+> > > PCI/ASPM: Add pci_enable_link_state()
+> > >
+> > > drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++----------
+> > > drivers/pci/pcie/aspm.c | 54 ++++++++++++++++++++
+> > > include/linux/pci.h | 7 +++
+> > > 3 files changed, 131 insertions(+), 26 deletions(-)
+> > >
+> > >
+> > > base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
+> >
+> >
+> > Regards,
+> > You-Sheng Yang
+> >
+>
+
+
+--
+Regards,
+You-Sheng Yang
+
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+Message-ID: <8b8c7ae512291532ea227b8a1c3f87c460e11e2f.camel@ljones.dev>
+Subject: Re: [PATCH V8 0/4] PCI: vmd: Enable PCIe ASPM and LTR on select
+ hardware
+From: Luke Jones <luke@ljones.dev>
+To: "David E. Box" <david.e.box@linux.intel.com>,
+ nirmal.patel@linux.intel.com, jonathan.derrick@linux.dev,
+ lorenzo.pieralisi@arm.com, hch@infradead.org, kw@linux.com,
+ robh@kernel.org, bhelgaas@google.com, michael.a.bottini@intel.com,
+ rafael@kernel.org, me@adhityamohan.in
+Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
+Date: Wed, 07 Dec 2022 22:05:28 +1300
+In-Reply-To: <20221103021822.308586-1-david.e.box@linux.intel.com>
+References: <20221103021822.308586-1-david.e.box@linux.intel.com>
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+
+On Wed, 2022-11-02 at 19:18 -0700, David E. Box wrote:
+> This series adds a work around for enabling PCIe ASPM and for setting
+> PCIe
+> LTR values on VMD reserved root ports on select platforms. While
+> configuration of these capabilities is usually done by BIOS, on these
+> platforms these capabilities will not be configured because the ports
+> are
+> not visible to BIOS. This was part of an initial design that expected
+> the
+> driver to completely handle the ports, including power management.
+> However
+> on Linux those ports are still managed by the PCIe core, which has
+> the
+> expectation that they adhere to device standards including BIOS
+> configuration, leading to this problem.
+>=20
+> The target platforms are Tiger Lake, Alder Lake, and Raptor Lake
+> though the
+> latter has already implemented support for configuring the LTR
+> values.
+> Meteor Lake is expected add BIOS ASPM support, eliminating the future
+> need
+> for this work around.
+>=20
+> Note, the driver programs the LTRs because BIOS would also normally
+> do this
+> for devices that do not set them by default. Without this, SoC power
+> management would be blocked on those platform. This SoC specific
+> value is
+> the maximum latency required to allow the SoC to enter the deepest
+> power
+> state.
+>=20
+> This patch addresses the following open bugzillas on VMD enabled
+> laptops
+> that cannot enter low power states.
+>=20
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D212355
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D215063
+> Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D213717
+>=20
+> David E. Box (3):
+> =C2=A0 PCI: vmd: Use PCI_VDEVICE in device list
+> =C2=A0 PCI: vmd: Create feature grouping for client products
+> =C2=A0 PCI: vmd: Add quirk to configure PCIe ASPM and LTR
+>=20
+> Michael Bottini (1):
+> =C2=A0 PCI/ASPM: Add pci_enable_link_state()
+>=20
+> =C2=A0drivers/pci/controller/vmd.c | 96 ++++++++++++++++++++++++++-------=
+-
+> --
+> =C2=A0drivers/pci/pcie/aspm.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 54 ++++++++=
+++++++++++++
+> =C2=A0include/linux/pci.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
+=C2=A0 |=C2=A0 7 +++
+> =C2=A03 files changed, 131 insertions(+), 26 deletions(-)
+>=20
+>=20
+> base-commit: 247f34f7b80357943234f93f247a1ae6b6c3a740
+
+I'd like to confirm that this patch series solves the VMD power issues
+present on the ASUS ROG M16 (GU603) laptop range (PCI dev ID =3D 467f).
+
+The difference is quite drastic.
+
+