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From a83315923e87a169ceb6c839a84ee0455868218f Mon Sep 17 00:00:00 2001
From: Prike Liang <Prike.Liang@amd.com>
Date: Tue, 25 May 2021 10:48:59 +0800
Subject: [PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3
for s2idle
In the NVMe controller default suspend mode use APST do the power state
suspend and resume and the NVMe remains in D0 during s2idle entry.Then the
NVMe device will be shutdown by firmware in the s0ix entry and will not
restore the third-party NVMe device power context in the firmware s0ix
resume. Finally,the NVMe will lost the power state during s2idle resume
and result in request queue timeout. So far,this issue only found on the
Renoir/Lucienne/Cezanne series and can be addressed by shutdown the NVMe
device in the s2idle entry.
Link:https://lore.kernel.org/stable/20210416155653.GA31818@redsun51.ssa.fujisawa.hgst.com/T/
Suggested-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/nvme/host/pci.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index c92a15c3fbc5..07198b6d6066 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -26,6 +26,9 @@
#include <linux/io-64-nonatomic-hi-lo.h>
#include <linux/sed-opal.h>
#include <linux/pci-p2pdma.h>
+#ifdef CONFIG_X86
+#include <asm/cpu_device_id.h>
+#endif
#include "trace.h"
#include "nvme.h"
@@ -2832,6 +2835,16 @@ static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
}
#ifdef CONFIG_ACPI
+
+#ifdef CONFIG_X86
+static const struct x86_cpu_id storage_d3_cpu_ids[] = {
+ X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL), /*Cezanne*/
+ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /*Renoir*/
+ X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL),/*Lucienne*/
+ {}
+};
+#endif
+
static bool nvme_acpi_storage_d3(struct pci_dev *dev)
{
struct acpi_device *adev;
@@ -2840,6 +2853,13 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
acpi_status status;
u8 val;
+#ifdef CONFIG_X86
+ /*
+ * Set the NVMe on the target platform to D3 directly by kernel power management.
+ */
+ if (x86_match_cpu(storage_d3_cpu_ids) && pm_suspend_default_s2idle())
+ return true;
+#endif
/*
* Look for _DSD property specifying that the storage device on the port
* must use D3 to support deep platform power savings during
--
GitLab
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