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-rw-r--r--.SRCINFO4
-rw-r--r--PKGBUILD6
-rw-r--r--fast_cppc.patch64
3 files changed, 72 insertions, 2 deletions
diff --git a/.SRCINFO b/.SRCINFO
index 6d0e3bd35c4b..f84fdbadab5f 100644
--- a/.SRCINFO
+++ b/.SRCINFO
@@ -1,6 +1,6 @@
pkgbase = linux-amd
pkgver = 6.8.v.8
- pkgrel = 1
+ pkgrel = 2
url = https://www.kernel.org/
arch = x86_64
license = GPL2
@@ -17,9 +17,11 @@ pkgbase = linux-amd
source = git+https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git#tag=v6.8.8
source = config.x86_64
source = https://raw.githubusercontent.com/graysky2/kernel_compiler_patch/20240221.2/more-uarches-for-kernel-6.8-rc4+.patch
+ source = fast_cppc.patch
sha256sums = SKIP
sha256sums = 5330fce19698bef9deb603bb20addc1abf137ad9f4dbdad57587228e3f69e713
sha256sums = d69232afd0dd6982ae941cf2d1f577f4be2011e3bb847d1db37952acf416b5d3
+ sha256sums = f8a69166a3ee91b797198b4e82b6e397a8f7749feed8aed7f3b323b020798a66
pkgname = linux-amd
pkgdesc = Linux kernel aimed at the ZNVER4/MZEN4 AMD Ryzen CPU based hardware
diff --git a/PKGBUILD b/PKGBUILD
index 646feffc8406..d27ca39f6e7d 100644
--- a/PKGBUILD
+++ b/PKGBUILD
@@ -6,7 +6,7 @@ gitver=v6.8.8
patchver=20240221.2
patchname=more-uarches-for-kernel-6.8-rc4+.patch
pkgver=6.8.v.8
-pkgrel=1
+pkgrel=2
arch=('x86_64')
url="https://www.kernel.org/"
license=('GPL2')
@@ -18,12 +18,16 @@ source=("git+https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git#ta
'config.x86_64'
# patch from our graysky archlinux colleague
"https://raw.githubusercontent.com/graysky2/kernel_compiler_patch/$patchver/$patchname"
+ # fast cppc patch
+ 'fast_cppc.patch'
)
sha256sums=('SKIP'
#config.x86_64
'5330fce19698bef9deb603bb20addc1abf137ad9f4dbdad57587228e3f69e713'
#grayskypatch
'd69232afd0dd6982ae941cf2d1f577f4be2011e3bb847d1db37952acf416b5d3'
+ #fast cppc patch
+ 'f8a69166a3ee91b797198b4e82b6e397a8f7749feed8aed7f3b323b020798a66'
)
_kernelname=${pkgbase#linux}
diff --git a/fast_cppc.patch b/fast_cppc.patch
new file mode 100644
index 000000000000..ff8fc5c14b03
--- /dev/null
+++ b/fast_cppc.patch
@@ -0,0 +1,64 @@
+From 2416f3b172dd3ac0d1c7a6371f6a14da8d5f5ed6 Mon Sep 17 00:00:00 2001
+From: Eggz <egnappah@gmail.com>
+Date: Mon, 29 Apr 2024 10:36:29 +0200
+Subject: [PATCH 1/1] Enable Fast CPPC
+
+Signed-off-by: Eggz <egnappah@gmail.com>
+---
+ arch/x86/include/asm/cpufeatures.h | 1 +
+ arch/x86/kernel/cpu/scattered.c | 1 +
+ drivers/cpufreq/amd-pstate.c | 7 ++++++-
+ 3 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
+index 76b3b00ff102..653d13b06ea3 100644
+--- a/arch/x86/include/asm/cpufeatures.h
++++ b/arch/x86/include/asm/cpufeatures.h
+@@ -466,6 +466,7 @@
+ #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */
+ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
+ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
++#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */
+
+ /*
+ * BUG word(s)
+diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
+index 0ebca40dfd74..cc66cca52b17 100644
+--- a/arch/x86/kernel/cpu/scattered.c
++++ b/arch/x86/kernel/cpu/scattered.c
+@@ -50,6 +50,7 @@ static const struct cpuid_bit cpuid_bits[] = {
+ { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
+ { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
+ { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 },
++ { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
+ { 0, 0, 0, 0, 0 }
+ };
+
+diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
+index 07f341995439..01897e81e3dc 100644
+--- a/drivers/cpufreq/amd-pstate.c
++++ b/drivers/cpufreq/amd-pstate.c
+@@ -49,6 +49,7 @@
+
+ #define AMD_PSTATE_TRANSITION_LATENCY 20000
+ #define AMD_PSTATE_TRANSITION_DELAY 1000
++#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
+
+ /*
+ * TODO: We need more time to fine tune processors with shared memory solution
+@@ -744,7 +745,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
+ }
+
+ policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY;
+- policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
++
++ if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC))
++ policy->transition_delay_us = AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY;
++ else
++ policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
+
+ policy->min = min_freq;
+ policy->max = max_freq;
+--
+2.44.0
+