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Package Details: sv2v-git 0.0.r1.g4c3dcf5-1
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Git Clone URL: | https://aur.archlinux.org/sv2v-git.git (read-only, click to copy) |
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Package Base: | sv2v-git |
Description: | SystemVerilog to Verilog conversion |
Upstream URL: | https://github.com/zachjs/sv2v |
Licenses: | custom: BSD3 |
Submitter: | b1f6c1c4 |
Maintainer: | b1f6c1c4 |
Last Packager: | b1f6c1c4 |
Votes: | 0 |
Popularity: | 0.000000 |
First Submitted: | 2022-01-07 08:51 (UTC) |
Last Updated: | 2022-01-07 08:51 (UTC) |
Latest Comments
GTP commented on 2024-06-07 11:47 (UTC) (edited on 2024-06-07 12:11 (UTC) by GTP)
I tried installing this package with yay, but it fails to build for me. You can find the full output at https://pastebin.com/Z17vc2Gy Edit: it compiled successfully by manually following the procedure in the GitHub repo's readme, so maybe there's an error in the provided makefile.