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python-textx
|
4.0.1-1 |
0 |
0.00
|
Python library for building Domain-Specific Languages and parsers |
xiretza
|
2024-03-03 14:06 (UTC) |
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python-sphinxextensions
|
0.2.0-1 |
0 |
0.00
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Extensions for the Sphinx documentation tool |
xiretza
|
2021-07-12 12:27 (UTC) |
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python-simplematrixbotlib
|
2.11.0-1 |
0 |
0.00
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An easy to use bot library for the Matrix ecosystem written in Python |
xiretza
|
2024-03-03 14:34 (UTC) |
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python-sdf-timing-git
|
r118.5b9dc79-1 |
0 |
0.00
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Python library for working Standard Delay Format (SDF) Timing Annotation files |
xiretza
|
2021-04-13 17:22 (UTC) |
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python-rapidyaml-git
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0.5.0.r14.g6a5a07f-1 |
2 |
0.00
|
A library to parse and emit YAML, and do it fast. |
xiretza
|
2023-05-14 13:45 (UTC) |
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python-quicklogic-fasm-utils-git
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r13.3d6a375-1 |
0 |
0.00
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A set of tools for creating FASM assemblers for the Symbiflow project |
xiretza
|
2022-05-14 18:04 (UTC) |
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python-quicklogic-fasm-git
|
r56.fafa623-1 |
0 |
0.00
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Tools, scripts and resources for generating a bitstream from FASM files for QuickLogic FPGAs |
xiretza
|
2022-05-14 18:03 (UTC) |
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python-pyvhdlmodel-git
|
0.25.1.r0.g3776f27-2 |
0 |
0.00
|
An abstract VHDL language model written in Python |
xiretza
|
2023-05-07 16:10 (UTC) |
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python-pytooling
|
6.1.0-1 |
0 |
0.00
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A powerful collection of arbitrary useful classes, decorators, meta-classes and exceptions |
xiretza
|
2024-05-01 15:45 (UTC) |
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python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
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Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-serv-git
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2020.08.r38.g2428c0c-1 |
1 |
0.00
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Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-rocket-git
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2020.08.r1.gfe810b8-1 |
1 |
0.00
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Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-picorv32-git
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2020.08.r1.g8bdce32-1 |
0 |
0.00
|
Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
|
python-pythondata-cpu-mor1kx-git
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2020.08.r3.gff01892-1 |
0 |
0.00
|
Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
|
python-pythondata-cpu-minerva-git
|
2020.08.r4.g2a69b7f-1 |
0 |
0.00
|
Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
|
python-pythondata-cpu-microwatt-git
|
2020.08.r219.gd695ff9-1 |
0 |
0.00
|
Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
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python-pythondata-cpu-lm32-git
|
2020.08.r1.g6344000-1 |
0 |
0.00
|
Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
|
python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
|
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
|
python-pythondata-cpu-blackparrot-git
|
2020.08.r18.gba50883f-1 |
0 |
0.00
|
Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
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python-pyghdl-git
|
3.0.0.r193.97df73f72-1 |
0 |
0.00
|
Python binding for GHDL and high-level APIs |
xiretza
|
2023-05-09 19:40 (UTC) |
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python-pydecor-git
|
2.0.0.r11.gd506ca8-1 |
0 |
0.00
|
Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
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python-pyattributes
|
2.5.1-1 |
0 |
0.00
|
Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |
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python-prjxray-git
|
r3800.3418f9b5-1 |
0 |
0.00
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Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
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python-litex-git
|
2020.04.r867.g5097b7ae-1 |
0 |
0.00
|
A Migen/MiSoC based Core/SoC builder |
xiretza
|
2020-11-17 11:41 (UTC) |
|
python-litex-boards-git
|
2020.12.r26.gbee71da-1 |
0 |
0.00
|
LiteX supported boards |
xiretza
|
2021-01-22 08:58 (UTC) |