aiger
|
1.9.9-2 |
0 |
0.00
|
A format, library and set of utilities for And-Inverter Graphs (AIGs) |
xiretza
|
2020-09-28 18:16 (UTC) |
boolector-git
|
3.2.2.r18.g1a89c229-1 |
0 |
0.00
|
A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions |
xiretza
|
2022-05-03 13:12 (UTC) |
f4pga-arch-defs-nightly-bin-toolchain
|
20220523.934b12d-1 |
0 |
0.00
|
Supporting scripts and data for the F4PGA toolchain |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-arch-defs-nightly-bin-device-xc7a50t
|
20220523.934b12d-1 |
0 |
0.00
|
F4PGA device definitions for xc7a50t |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-arch-defs-nightly-bin-device-xc7a100t
|
20220523.934b12d-1 |
0 |
0.00
|
F4PGA device definitions for xc7a100t |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-arch-defs-nightly-bin-device-xc7a200t
|
20220523.934b12d-1 |
0 |
0.00
|
F4PGA device definitions for xc7a200t |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-arch-defs-nightly-bin-device-xc7z010
|
20220523.934b12d-1 |
0 |
0.00
|
F4PGA device definitions for xc7z010 |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-arch-defs-nightly-bin-device-xc7z020
|
20220523.934b12d-1 |
0 |
0.00
|
F4PGA device definitions for xc7z020 |
xiretza
|
2022-06-01 09:58 (UTC) |
f4pga-git
|
r781.5c805fa-2 |
0 |
0.00
|
F4PGA tools |
xiretza
|
2022-06-03 17:05 (UTC) |
flatbuffers-git
|
1:2.0.6.r130.g6e279164-1 |
0 |
0.00
|
An efficient cross platform serialization library for C++, with support for Java, C# and Go |
xiretza
|
2022-07-31 15:45 (UTC) |
python-flatbuffers-git
|
1:2.0.6.r130.g6e279164-1 |
0 |
0.00
|
An efficient cross platform serialization library for Python |
xiretza
|
2022-07-31 15:45 (UTC) |
fpga-interchange-schema-git
|
r22.cb6d168-2 |
0 |
0.00
|
FPGA interchange schema definitions |
xiretza
|
2021-03-17 19:36 (UTC) |
lemonldap-ng
|
2.0.16-1 |
0 |
0.00
|
A modular WebSSO (Single Sign On) based on Apache::Session modules |
xiretza
|
2023-03-12 17:30 (UTC) |
libargparse-git
|
r69.ee74d1b-1 |
0 |
0.00
|
A C++ command-line parsing library |
xiretza
|
2021-12-29 11:05 (UTC) |
libmirisdr4-v1
|
1.1.2-1 |
0 |
0.00
|
Support of Mirics MSi001 + MSi2500 SDR devices (yet another flavour of libmirisdr) (version 1.x) |
xiretza
|
2022-05-06 12:21 (UTC) |
libtg_owt-git
|
0.git.r397.afd9d5d3-1 |
0 |
0.00
|
WebRTC library - static linked, git version |
xiretza
|
2024-03-03 19:10 (UTC) |
openelp-git
|
0.8.0.r8.g48f77d1-1 |
0 |
0.00
|
An open source EchoLink proxy for Linux and Windows |
xiretza
|
2020-12-31 14:54 (UTC) |
perl-apache-session
|
1.94-3 |
0 |
0.00
|
A persistence framework for session data |
xiretza
|
2022-06-01 16:25 (UTC) |
perl-convert-base32
|
0.06-5 |
0 |
0.00
|
Encoding and decoding of base32 strings |
xiretza
|
2022-06-01 16:27 (UTC) |
perl-crypt-openssl-x509
|
1.915-1 |
0 |
0.00
|
Perl extension to OpenSSL's X509 API |
xiretza
|
2023-06-19 19:15 (UTC) |
perl-gd-securityimage
|
1.75-5 |
0 |
0.00
|
Security image (captcha) generator |
xiretza
|
2022-06-01 16:31 (UTC) |
prjxray-db-git
|
r244.057e179-2 |
0 |
0.00
|
Project X-Ray (Xilinx 7-series bit-stream format) database |
xiretza
|
2021-01-22 21:07 (UTC) |
prjxray-tools-git
|
r3800.3418f9b5-1 |
0 |
0.00
|
Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
python-prjxray-git
|
r3800.3418f9b5-1 |
0 |
0.00
|
Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
python-cmake-build-extension-git
|
0.5.1.r13.g856f0e0-1 |
0 |
0.00
|
Setuptools extension to build and package CMake projects |
xiretza
|
2023-05-18 10:57 (UTC) |
python-constraint-git
|
2.0.0b3.r10.g2357471-1 |
0 |
0.00
|
Solvers for Constraint Satisfaction Problems (CSPs) over finite domains in simple and pure Python |
xiretza
|
2023-09-24 14:23 (UTC) |
python-fasm-git
|
0.0.2.r98.g9a73d70-4 |
0 |
0.00
|
FPGA Assembly (FASM) Parser and Generation library |
xiretza
|
2022-06-17 07:56 (UTC) |
python-itertree
|
1.0.5-1 |
0 |
0.00
|
Python tree structure for data storage and iterations |
xiretza
|
2023-07-16 14:47 (UTC) |
python-litedram-git
|
2020.08.r101.g1117068-1 |
0 |
0.00
|
A small footprint and configurable DRAM core for LiteX |
xiretza
|
2020-11-17 11:39 (UTC) |
python-liteeth-git
|
2020.04.r34.g0624256-1 |
0 |
0.00
|
A small footprint and configurable Ethernet core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-liteiclink-git
|
2020.08.r83.g3d1165b-1 |
0 |
0.00
|
Small footprint and configurable inter chip communication cores for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-litejesd204b-git
|
2020.08.r1.g1e88fa8-1 |
0 |
0.00
|
A small footprint and configurable JESD204B core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-litepcie-git
|
2020.08.r40.g5e88ab6-1 |
0 |
0.00
|
A small footprint and configurable PCIe core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-litesata-git
|
2020.08.r66.ge850b72-1 |
0 |
0.00
|
A small footprint and configurable SATA core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-litescope-git
|
2020.08.r10.g94e2d15-1 |
0 |
0.00
|
A small footprint and configurable embedded logic analyzer for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
python-litesdcard-git
|
2020.08.r14.g9e267a5-1 |
0 |
0.00
|
A small footprint and configurable SDCard core for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
python-litevideo-git
|
2020.04.r0.g41f3014-1 |
0 |
0.00
|
Small footprint and configurable video cores for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
python-litex-boards-git
|
2020.12.r26.gbee71da-1 |
0 |
0.00
|
LiteX supported boards |
xiretza
|
2021-01-22 08:58 (UTC) |
python-litex-git
|
2020.04.r867.g5097b7ae-1 |
0 |
0.00
|
A Migen/MiSoC based Core/SoC builder |
xiretza
|
2020-11-17 11:41 (UTC) |
python-pyattributes
|
2.5.1-1 |
0 |
0.00
|
Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |
python-pydecor-git
|
2.0.0.r11.gd506ca8-1 |
0 |
0.00
|
Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
python-pyghdl-git
|
3.0.0.r193.97df73f72-1 |
0 |
0.00
|
Python binding for GHDL and high-level APIs |
xiretza
|
2023-05-09 19:40 (UTC) |
python-pythondata-cpu-blackparrot-git
|
2020.08.r18.gba50883f-1 |
0 |
0.00
|
Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
|
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-lm32-git
|
2020.08.r1.g6344000-1 |
0 |
0.00
|
Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-microwatt-git
|
2020.08.r219.gd695ff9-1 |
0 |
0.00
|
Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-pythondata-cpu-minerva-git
|
2020.08.r4.g2a69b7f-1 |
0 |
0.00
|
Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
python-pythondata-cpu-mor1kx-git
|
2020.08.r3.gff01892-1 |
0 |
0.00
|
Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-pythondata-cpu-picorv32-git
|
2020.08.r1.g8bdce32-1 |
0 |
0.00
|
Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
|
Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |