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openelp-git
|
0.8.0.r8.g48f77d1-1 |
0 |
0.00
|
An open source EchoLink proxy for Linux and Windows |
xiretza
|
2020-12-31 14:54 (UTC) |
|
osm2pgsql-git
|
1.8.1.r175.g1cfb05be-1 |
7 |
0.00
|
tool for loading OpenStreetMap data into a PostgreSQL / PostGIS database |
xiretza
|
2023-07-16 14:42 (UTC) |
|
outrun-git
|
r3.1e86c42-1 |
1 |
0.00
|
Execute a local command using the processing power of another Linux machine |
xiretza
|
2021-03-18 23:51 (UTC) |
|
perl-apache-session
|
1.94-3 |
0 |
0.00
|
A persistence framework for session data |
xiretza
|
2022-06-01 16:25 (UTC) |
|
perl-class-errorhandler
|
0.04-4 |
4 |
0.00
|
Base class for error handling |
xiretza
|
2022-06-01 16:26 (UTC) |
|
perl-convert-base32
|
0.06-5 |
0 |
0.00
|
Encoding and decoding of base32 strings |
xiretza
|
2022-06-01 16:27 (UTC) |
|
perl-convert-pem
|
0.08-5 |
1 |
0.00
|
Read/write encrypted ASN.1 PEM files |
xiretza
|
2022-06-01 16:28 (UTC) |
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perl-crypt-openssl-x509
|
1.915-1 |
0 |
0.00
|
Perl extension to OpenSSL's X509 API |
xiretza
|
2023-06-19 19:15 (UTC) |
|
perl-gd-securityimage
|
1.75-5 |
0 |
0.00
|
Security image (captcha) generator |
xiretza
|
2022-06-01 16:31 (UTC) |
|
prjtrellis-git
|
1.2.1.r4.g64b38df-2 |
7 |
0.00
|
Tools for working with the Lattice ECP5 bit-stream format |
xiretza
|
2022-06-27 18:08 (UTC) |
|
prjxray-db-git
|
r244.057e179-2 |
0 |
0.00
|
Project X-Ray (Xilinx 7-series bit-stream format) database |
xiretza
|
2021-01-22 21:07 (UTC) |
|
prjxray-tools-git
|
r3800.3418f9b5-1 |
0 |
0.00
|
Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
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python-amaranth-boards-git
|
r208.2d0a23b-1 |
1 |
0.00
|
Board definitions for Amaranth HDL |
xiretza
|
2022-04-24 07:58 (UTC) |
|
python-amaranth-git
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0.3.r19.g8b85afa-3 |
2 |
0.00
|
A modern hardware definition language and toolchain based on Python (formerly nMigen) |
xiretza
|
2022-04-24 07:48 (UTC) |
|
python-cmake-build-extension-git
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0.5.1.r13.g856f0e0-1 |
0 |
0.00
|
Setuptools extension to build and package CMake projects |
xiretza
|
2023-05-18 10:57 (UTC) |
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python-constraint-git
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2.0.0b3.r10.g2357471-1 |
0 |
0.00
|
Solvers for Constraint Satisfaction Problems (CSPs) over finite domains in simple and pure Python |
xiretza
|
2023-09-24 14:23 (UTC) |
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python-cryptography-fernet-wrapper
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1.0.3-2 |
1 |
0.00
|
A wrapper for cryptography.fernet |
xiretza
|
2023-09-17 11:45 (UTC) |
|
python-fasm-git
|
0.0.2.r98.g9a73d70-4 |
0 |
0.00
|
FPGA Assembly (FASM) Parser and Generation library |
xiretza
|
2022-06-17 07:56 (UTC) |
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python-flatbuffers-git
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1:2.0.6.r130.g6e279164-1 |
0 |
0.00
|
An efficient cross platform serialization library for Python |
xiretza
|
2022-07-31 15:45 (UTC) |
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python-gpsoauth
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1.0.4-1 |
2 |
0.00
|
A python client library for Google Play Services OAuth. |
xiretza
|
2024-03-03 14:36 (UTC) |
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python-itertree
|
1.0.5-1 |
0 |
0.00
|
Python tree structure for data storage and iterations |
xiretza
|
2023-07-16 14:47 (UTC) |
|
python-litedram-git
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2020.08.r101.g1117068-1 |
0 |
0.00
|
A small footprint and configurable DRAM core for LiteX |
xiretza
|
2020-11-17 11:39 (UTC) |
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python-liteeth-git
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2020.04.r34.g0624256-1 |
0 |
0.00
|
A small footprint and configurable Ethernet core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-liteiclink-git
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2020.08.r83.g3d1165b-1 |
0 |
0.00
|
Small footprint and configurable inter chip communication cores for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litejesd204b-git
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2020.08.r1.g1e88fa8-1 |
0 |
0.00
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A small footprint and configurable JESD204B core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litepcie-git
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2020.08.r40.g5e88ab6-1 |
0 |
0.00
|
A small footprint and configurable PCIe core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litesata-git
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2020.08.r66.ge850b72-1 |
0 |
0.00
|
A small footprint and configurable SATA core for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litescope-git
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2020.08.r10.g94e2d15-1 |
0 |
0.00
|
A small footprint and configurable embedded logic analyzer for LiteX |
xiretza
|
2020-11-17 11:40 (UTC) |
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python-litesdcard-git
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2020.08.r14.g9e267a5-1 |
0 |
0.00
|
A small footprint and configurable SDCard core for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-litevideo-git
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2020.04.r0.g41f3014-1 |
0 |
0.00
|
Small footprint and configurable video cores for LiteX |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-litex-boards-git
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2020.12.r26.gbee71da-1 |
0 |
0.00
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LiteX supported boards |
xiretza
|
2021-01-22 08:58 (UTC) |
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python-litex-git
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2020.04.r867.g5097b7ae-1 |
0 |
0.00
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A Migen/MiSoC based Core/SoC builder |
xiretza
|
2020-11-17 11:41 (UTC) |
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python-prjxray-git
|
r3800.3418f9b5-1 |
0 |
0.00
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Documenting the Xilinx 7-series bit-stream format |
xiretza
|
2023-09-24 12:59 (UTC) |
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python-pyattributes
|
2.5.1-1 |
0 |
0.00
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Implementations of .NET-like attributes realized with Python decorators |
xiretza
|
2022-03-08 20:46 (UTC) |
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python-pydecor-git
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2.0.0.r11.gd506ca8-1 |
0 |
0.00
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Easy-peasy Python decorators |
xiretza
|
2021-02-10 14:19 (UTC) |
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python-pyghdl-git
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3.0.0.r193.97df73f72-1 |
0 |
0.00
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Python binding for GHDL and high-level APIs |
xiretza
|
2023-05-09 19:40 (UTC) |
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python-pythondata-cpu-blackparrot-git
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2020.08.r18.gba50883f-1 |
0 |
0.00
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Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
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python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
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Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
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python-pythondata-cpu-lm32-git
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2020.08.r1.g6344000-1 |
0 |
0.00
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Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
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python-pythondata-cpu-microwatt-git
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2020.08.r219.gd695ff9-1 |
0 |
0.00
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Python module containing vhdl files for microwatt cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
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python-pythondata-cpu-minerva-git
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2020.08.r4.g2a69b7f-1 |
0 |
0.00
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Python module containing sources files for minerva cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
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python-pythondata-cpu-mor1kx-git
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2020.08.r3.gff01892-1 |
0 |
0.00
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Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
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python-pythondata-cpu-picorv32-git
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2020.08.r1.g8bdce32-1 |
0 |
0.00
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Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
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python-pythondata-cpu-rocket-git
|
2020.08.r1.gfe810b8-1 |
1 |
0.00
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Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-serv-git
|
2020.08.r38.g2428c0c-1 |
1 |
0.00
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Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
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Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
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python-pytooling
|
6.0.1-1 |
0 |
0.00
|
A powerful collection of arbitrary useful classes, decorators, meta-classes and exceptions |
xiretza
|
2024-03-03 14:46 (UTC) |
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python-pyvhdlmodel-git
|
0.25.1.r0.g3776f27-2 |
0 |
0.00
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An abstract VHDL language model written in Python |
xiretza
|
2023-05-07 16:10 (UTC) |
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python-quicklogic-fasm-git
|
r56.fafa623-1 |
0 |
0.00
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Tools, scripts and resources for generating a bitstream from FASM files for QuickLogic FPGAs |
xiretza
|
2022-05-14 18:03 (UTC) |
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python-quicklogic-fasm-utils-git
|
r13.3d6a375-1 |
0 |
0.00
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A set of tools for creating FASM assemblers for the Symbiflow project |
xiretza
|
2022-05-14 18:04 (UTC) |