verible-bin
|
0.0.3622-1 |
2 |
0.57
|
SystemVerilog parser, linter, formatter and etc from Google |
ildus
|
2024-03-23 07:09 (UTC) |
veridian-bin
|
0.0.0-5 |
1 |
0.02
|
A SystemVerilog Language Server |
kalex
|
2024-03-21 08:30 (UTC) |
svls
|
0.2.11-1 |
4 |
0.02
|
SystemVerilog language server |
otreblan
|
2024-02-11 20:30 (UTC) |
python-vunit_hdl
|
4.7.0-1 |
2 |
0.01
|
Unit Testing Framework for VHDL/SystemVerilog |
smallAndSimple
|
2023-05-14 09:40 (UTC) |
slang-verilog
|
6.0-2 |
3 |
0.00
|
SystemVerilog Language Services |
jrudess
|
2024-04-25 02:42 (UTC) |
iverilog-git
|
s20150603.r1490.g0a86773c5-1 |
2 |
0.00
|
Icarus Verilog simulation and synthesis tool |
gilcu3
|
2022-05-02 09:06 (UTC) |
istyle-verilog-formatter-git
|
v1.23.r0.g3ec7507-1 |
1 |
0.00
|
Fast and Free Automatic Formatter for Verilog Source Code |
joposter
|
2021-06-04 09:11 (UTC) |
verilog-format-git
|
c169dd4-1 |
2 |
0.00
|
Console application for apply format to verilog file. |
playercc
|
2021-06-22 11:39 (UTC) |
yosys-uhdm-plugin
|
924fe98-1 |
0 |
0.00
|
UDHM plugin for Yosys (SystemVerilog support) |
ildus
|
2023-01-19 11:43 (UTC) |
vim-systemverilog-git
|
r17.27d89e8-1 |
0 |
0.00
|
SystemVerilog support for vim |
anatolik
|
2015-11-30 22:46 (UTC) |
vhd2vl-git
|
2.5-1 |
1 |
0.00
|
Translate synthesizable VHDL into Verilog 2001 |
marzoul
|
2021-02-06 17:15 (UTC) |
veriwell
|
2.8.7-1 |
6 |
0.00
|
The Verilog Simulator |
anatolik
|
2015-06-17 15:54 (UTC) |
verilogx
|
0.1-1 |
0 |
0.00
|
A simple, easy, and fast Verilog simulator. |
rafiibrahim8
|
2022-04-24 17:37 (UTC) |
verilator-git
|
r5486.0e4da3b0b-1 |
0 |
0.00
|
The fastest free Verilog HDL simulator |
Sequencer
|
2022-10-22 07:10 (UTC) |
verible-git
|
0.0.r558.7fbda6835f-2 |
2 |
0.00
|
SystemVerilog parser, style-linter, and formatter |
accuminium
|
2023-11-11 21:04 (UTC) |
verible
|
0.0r2037.g4cccc6b2-1 |
1 |
0.00
|
SystemVerilog(Verilog) Parser, Style-Linter, and Formatter from Google |
nullik
|
2022-03-19 11:44 (UTC) |
v2x-git
|
0.0.r616.g1325cb3-1 |
0 |
0.00
|
A tool for converting specialized annotated Verilog models into XML |
xiretza
|
2022-05-14 18:46 (UTC) |
uvm-python-git
|
r1174.26acd2b-1 |
0 |
0.00
|
Port of SystemVerilog Universal Verification Methodology (UVM) 1.2 to Python and cocotb |
mox
|
2021-03-06 11:44 (UTC) |
uhdm-git
|
r2067.496bb31-1 |
0 |
0.00
|
A complete modeling of the IEEE SystemVerilog Object Model |
xiretza
|
2023-09-24 19:59 (UTC) |
tree-sitter-verilog-git
|
0.0.r316.g9020313-1 |
0 |
0.00
|
SystemVerilog grammar for tree-sitter |
Chocobo1
|
2024-01-28 09:11 (UTC) |
svlint-bin
|
0.9.2-1 |
0 |
0.00
|
SystemVerilog linter compliant with IEEE1800-2017 |
snafu
|
2024-04-24 13:18 (UTC) |
svlint
|
0.8.0-1 |
0 |
0.00
|
SystemVerilog linter compliant with IEEE1800-2017 |
Freed
|
2023-07-17 19:34 (UTC) |
svlangserver
|
0.4.0-1 |
0 |
0.00
|
A language server for systemverilog |
h313
|
2022-05-03 06:05 (UTC) |
sv2v-git
|
0.0.r1.g4c3dcf5-1 |
0 |
0.00
|
SystemVerilog to Verilog conversion |
b1f6c1c4
|
2022-01-07 08:51 (UTC) |
sv2v
|
0.0.11-1 |
1 |
0.00
|
SystemVerilog to Verilog conversion |
yrlf
|
2023-12-04 00:00 (UTC) |
surelog-git
|
1.75.r1.ge83d01f-1 |
0 |
0.00
|
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. |
xiretza
|
2023-09-24 20:37 (UTC) |
sigasi
|
5.5.0-1 |
5 |
0.00
|
Eclipse-based commercial VHDL, Verilog and SystemVerilog IDE |
fredericva
|
2024-03-27 20:27 (UTC) |
python-pyuvm
|
2.9.1-1 |
0 |
0.00
|
pyuvm is the Universal Verification Methodology implemented in Python instead of SystemVerilog. pyuvm uses cocotb to interact with the simulator and schedule simulation events. |
m42uko
|
2023-10-13 11:59 (UTC) |
python-pythondata-cpu-vexriscv-git
|
2020.08.r1.g2962f4a-1 |
0 |
0.00
|
Python module containing verilog files for vexriscv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-serv-git
|
2020.08.r38.g2428c0c-1 |
1 |
0.00
|
Python module containing verilog files for serv cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-rocket-git
|
2020.08.r1.gfe810b8-1 |
1 |
0.00
|
Python module containing verilog files for rocket cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:55 (UTC) |
python-pythondata-cpu-picorv32-git
|
2020.08.r1.g8bdce32-1 |
0 |
0.00
|
Python module containing verilog files for picorv32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:53 (UTC) |
python-pythondata-cpu-mor1kx-git
|
2020.08.r3.gff01892-1 |
0 |
0.00
|
Python module containing verilog files for mor1kx cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:52 (UTC) |
python-pythondata-cpu-lm32-git
|
2020.08.r1.g6344000-1 |
0 |
0.00
|
Python module containing verilog files for lm32 cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-cv32e40p-git
|
2020.08.r1.gb8fe3c4-1 |
0 |
0.00
|
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX) |
xiretza
|
2020-11-17 11:50 (UTC) |
python-pythondata-cpu-blackparrot-git
|
2020.08.r18.gba50883f-1 |
0 |
0.00
|
Python module containing system_verilog files for blackparrot cpu (for use with LiteX) |
xiretza
|
2022-06-02 16:23 (UTC) |
python-cocotb-git
|
r3638.13a4c949-1 |
1 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
m42uko
|
2023-10-16 08:53 (UTC) |
python-cocotb-bus-git
|
r3101.a3e22f78-1 |
0 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
orphan
|
2021-06-03 10:58 (UTC) |
python-cocotb
|
1.8.1-1 |
3 |
0.00
|
Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python |
m42uko
|
2023-10-16 08:44 (UTC) |
oss-cvc-git
|
r11.d01c4ab-2 |
0 |
0.00
|
a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator |
tequa
|
2020-07-27 12:39 (UTC) |
ophidian-verilog-parser-git
|
0.2-2 |
0 |
0.00
|
A Flex/Bison parser for the IEEE 1364-2001 Verilog Standard. |
tarberd
|
2018-01-17 20:46 (UTC) |
openvaf
|
23.5.0-3 |
0 |
0.00
|
A Next-Generation Verilog-A compiler https://openvaf.semimod.de/ |
Zes4Null
|
2024-03-08 02:20 (UTC) |
gnucap-modelgen-verilog-git
|
develop-1 |
0 |
0.00
|
Verilog-AMS for Gnucap |
felixs
|
2023-06-10 15:42 (UTC) |
fomu-verilog-blink
|
0.1-1 |
0 |
0.00
|
Blink test for FOMU FPGA ? |
GNUtoo
|
2022-04-27 16:06 (UTC) |
elf2hex
|
20.08.00.00-13 |
0 |
0.00
|
SiFive's Verilog test harnesses can't directly read ELF binaries but are instead required to be provided with a hexidecimal dump of a particular width and depth. This project allows users to easily create these files. |
taotieren
|
2024-01-23 12:01 (UTC) |
covered
|
0.7.10-3 |
0 |
0.00
|
Verilog Code Coverage Analyzer |
tequa
|
2015-10-29 21:06 (UTC) |
adms-git
|
2.3.7.r25.gcadf421-1 |
8 |
0.00
|
ADMS is a codegenerator for the VERILOG-A(MS) language |
dreieck
|
2023-10-31 16:14 (UTC) |
adms
|
2.3.7-1 |
13 |
0.00
|
codegenerator for the VERILOG-A(MS) language |
bidulock
|
2020-12-09 00:09 (UTC) |