netlistsvg-git
|
1.0.2.r10.g752549e-1 |
2 |
0.00
|
Draws an SVG schematic from a yosys JSON netlist |
thotypous
|
2023-06-10 04:48 (UTC) |
yosys-git
|
0.19+20.r11686.12b0ce972-1 |
17 |
0.00
|
A framework for RTL synthesis |
thasti
|
2022-07-22 20:33 (UTC) |
yosys-uhdm-plugin
|
924fe98-1 |
0 |
0.00
|
UDHM plugin for Yosys (SystemVerilog support) |
ildus
|
2023-01-19 11:43 (UTC) |
yosys-nightly
|
1:20240513_yosys_0.41_70_g07ac4c2fa-1 |
1 |
0.00
|
Yosys Open SYnthesis Suite, A framework for RTL synthesis |
lethalbit
|
2024-05-13 00:00 (UTC) |
yosys-f4pga-plugins-git
|
1.20230906.r3.g7c89a55-1 |
0 |
0.00
|
Plugins for Yosys developed as part of the F4PGA project. |
xiretza
|
2023-09-24 20:38 (UTC) |
symbiyosys-nightly
|
1:5d19e46_20211125-1 |
0 |
0.00
|
Front-end for Yosys-based formal verification flows |
lethalbit
|
2021-11-25 00:00 (UTC) |
symbiyosys-git
|
r284.ac9001b-1 |
3 |
0.00
|
A front-end driver program for Yosys-based formal hardware verification flows |
benallard
|
2021-12-29 17:46 (UTC) |
sby-nightly
|
1:20240513_yosys_0.41_2_g641d5d5-1 |
0 |
0.00
|
Front-end for Yosys-based formal verification flows |
lethalbit
|
2024-05-13 00:00 (UTC) |
mcy-nightly
|
1:20240513_yosys_0.41_2_gb01592a-1 |
0 |
0.00
|
Mutation Cover with Yosys |
lethalbit
|
2024-05-13 00:00 (UTC) |
lsoracle-git
|
r358.febd1523-1 |
0 |
0.00
|
Logic Synthesis oracle (with yosys plugin enabled) |
fansp
|
2023-04-11 12:06 (UTC) |
ghdl-yosys-plugin-git
|
r219.5b64ccf-2 |
1 |
0.00
|
VHDL synthesis (based on ghdl and yosys) |
xiretza
|
2023-06-11 08:56 (UTC) |
eqy-nightly
|
1:20240513_yosys_0.41_3_g702af89-1 |
0 |
0.00
|
Equivalence Checking with Yosys |
lethalbit
|
2024-05-13 00:00 (UTC) |